DRV2605L-Q1：汽车触觉驱动器技术规格

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"TI-DRV2605L-Q1.pdf" 是一款专为汽车行业的LRA（线性谐振致动器）和ERM（偏轴转动惯量电机）设计的触觉驱动器。该器件集成了丰富的功能，如数字回放引擎、智能环路架构以及对多种致动器的支持，旨在提供高效且精准的触感反馈。 DRV2605L-Q1 符合汽车级应用标准，满足AEC-Q100第二级温度等级，适用于-40°C至105°C的工作环境，并具备HBM静电放电等级1B和CDM ESD分类等级C6的耐静电能力。它是一个高度灵活的解决方案，可驱动LRA和ERM来实现触觉反馈，适合各种汽车界面中的应用。此驱动器采用I2C接口进行控制，配备了数字回放引擎，包括波形序列器和触发器，支持实时回放模式和I2C双模式驱动。其智能环路架构采用专利控制算法，实现了自动过驱动和制动、谐振跟踪和报告（仅限LRA）、致动器诊断以及自动级别校准，确保了系统性能的稳定性和致动器的健康状态监测。此外，DRV2605L-Q1支持Immersion的TouchSense®2200特性，内置了Immersion的效果库，可以实现音频到振动的转换。它还具备驱动补偿功能，可以在电池放电过程中维持稳定的性能，工作电压范围广泛，从2V到5.2V，具有高效的差分开关输出驱动。该驱动器接受PWM输入，可调节0%至100%的占空比，还包含硬件触发输入，确保快速启动。这些特性使得DRV2605L-Q1成为汽车触觉反馈系统的理想选择。

DRV2605L-Q1

ZHCSEJ7B –OCTOBER 2015–REVISED APRIL 2018

www.ti.com.cn

Feature Description (continued)

7.3.2.5 Automatic Level Calibration

The smart-loop architecture uses actuator feedback by monitoring the back-EMF behavior of the actuator. The

level of back-EMF voltage can vary across actuator manufacturers because of the specific actuator construction.

Auto calibration compensates for the variation and also performs scaling for the desired actuator according to the

specified rated voltage and overdrive clamp-register settings. When auto calibration is performed, a 100% signal

level at any of the DRV2605L-Q1 input interfaces supplies the rated voltage to the actuator at steady-state. The

feedback allows the output level to increase above the rated voltage level for automatic overdrive and braking,

but without allowing the output level to exceed the programmable overdrive clamp voltage.

In the event where the automatic level-calibration routine fails, the DIAG_RESULT bit in register 0x00 is asserted

to flag the problem. Calibration failures are typically fixed by adjusting the registers associated with the automatic

level-calibration routine or, for LRA actuators, the registers associated with the automatic-resonance detection

engine. See the

器件和文档支持

section for automatic-level calibration programming.

7.3.2.5.1 Automatic Compensation for Resistive Losses

The DRV2605L-Q1 device automatically compensates for resistive losses in the driver. During the automatic

level-calibration routine, the impedance of the actuator is checked and the compensation factor is determined

and stored in the A_CAL_COMP[7:0] bit.

7.3.2.5.2 Automatic Back-EMF Normalization

The DRV2605L-Q1 device automatically compensates for differences in back-EMF magnitude between

actuators. The compensation factor is determined during the automatic level-calibration routine and the factor is

stored in the A_CAL_BEMF[7:0] bit.

7.3.2.5.3 Calibration Time Adjustment

The duration of the automatic level-calibration routine has an impact on accuracy. The impact is highly

dependent on the start-time characteristic of the actuator. The auto-calibration routine expects the actuator to

have reached a steady acceleration before the calibration factors are calculated. Because the start-time

characteristic can be different for each actuator, the AUTO_CAL_TIME[1:0] bit can change the duration of the

automatic level-calibration routine to optimize calibration performance.

7.3.2.5.4 Loop-Gain Control

The DRV2605L-Q1 device allows the user to control how fast the driver attempts to match the back-EMF (and

thus motor velocity) and the input signal level. Higher loop-gain (or faster settling) options result in less-stable

operation than lower loop gain (or slower settling). The LOOP_GAIN[1:0] bit controls the loop gain.

7.3.2.5.5 Back-EMF Gain Control

The BEMF_GAIN[1:0] bit sets the analog gain for the back-EMF amplifier. The auto-calibration routine

automatically populates the bit with the most appropriate value for the actuator.

Modifying the SAMPLE_TIME[1:0] bit also adjusts the back-EMF gain. The higher the sample time, the higher

the gain.

By default, the back-EMF is sampled once during a period. In the event that a twice per-period sampling is

desired, assert the LRA_DRIVE_MODE bit.

7.3.2.6 Actuator Diagnostics

The DRV2605L-Q1 device is capable of determining whether the actuator is not present (open) or shorted. If a

fault is detected during the diagnostic process, the DIAG_RESULT bit is asserted.

7.3.2.7 Automatic Re-Synchronization

For the LRA, the DRV2605L-Q1 device features an automatic re-synchronization mode which automatically

pushes the actuator in the correct direction when a waveform begins playing while the actuator is moving. If the

actuator is at rest when the waveform begins, the DRV2605L-Q1 device drives in the default direction.

ERM Library A

LIBRARY_SEL[2:0] = 1

ERM Library E

LIBRARY_SEL[2:0] = 5

LRA Library

LIBRARY_SEL[2:0] = 6

ERM Library F

LIBRARY_SEL[2:0] = 7

DRV2605L-Q1

www.ti.com.cn

ZHCSEJ7B –OCTOBER 2015–REVISED APRIL 2018

Feature Description (continued)

7.3.3 Open-Loop Operation for LRA

In the event that open-loop operation is desired (such as for off-resonance driving) the DRV2605L-Q1 device

includes an open-loop LRA drive mode that is available through the PWM input or through the digital interface.

When using the PWM input in open-loop mode, the DRV2605L-Q1 device employs a fixed divider that observes

the PWM signal and commutates the output drive signal at the PWM frequency divided by 128. To accomplish

LRA drive, the host should drive the PWM frequency at 128 times the desired operating frequency.

When activated, the digital open-loop mode is available for pre-stored waveforms as well as for RTP mode. The

OL_LRA_PERIOD bit in register 0x20 programs the operating frequency, which is derived from the PWM output

frequency, ƒ

O(PWM)

. Use Equation 1 to calculate the driving frequency. The open-loop mode does not receive the

benefits of the smart-loop architecture.

7.3.4 Open-Loop Operation for ERM

The DRV2605L-Q1 device offers ERM open-loop operation through the PWM input. The output voltage is based

on the duty cycle of the provided PWM signal, where the OD_CLAMP[7:0] bit in register 0x17 sets the full-scale

amplitude. For details see the Rated Voltage Programming section.

7.3.5 Flexible Front-End Interface

The DRV2605L-Q1 device offers multiple ways to launch and control haptic effects. The MODE[2:0] bit in register

0x01 is used to select the interface mode.

7.3.5.1 PWM Interface

When the DRV2605L-Q1 device is in PWM interface mode, the device accepts PWM data at the IN/TRIG pin.

The DRV2605L-Q1 device drives the actuator continuously in PWM interface mode until the user sets the device

to standby mode or to enter another interface mode. In standby mode, the strength of vibration is determined by

the duty cycle.

For the LRA, the DRV2605L-Q1 device automatically tracks the resonance frequency unless the

LRA_OPEN_LOOP bit in register 0x1D is set. If the LRA_OPEN_LOOP bit is set, the LRA is driven according to

the frequency of the PWM input signal. Specifically, the driving frequency is the PWM frequency divided by 128.

7.3.5.2 Internal Memory Interface

The DRV2605L-Q1 device has seven internal-ROM libraries designed by Immersion called TS2200. The first five

libraries and the last library are specifically tuned for six categories of ERMs operated in open-loop mode (see

Table 1). Library 6 is a closed-loop library tuned for LRAs. The library selection occurs through register 0x03 (see

the (Address: 0x03) section).

Figure 12. Library Selection

DRV2605L-Q1

ZHCSEJ7B –OCTOBER 2015–REVISED APRIL 2018

www.ti.com.cn

Feature Description (continued)

Table 1. ERM Library Table

LIBRARY RATED VOLTAGE OVERDRIVE VOLTAGE RISE TIME BRAKE TIME

A 1.3 V 3 V 40 ms to 60 ms 20 ms to 40 ms

B 3 V 3 V 40 ms to 60 ms 5 ms to 15 ms

C 3 V 3 V 60 ms to 80 ms 10 ms to 20 ms

D 3 V 3 V 100 ms to 140 ms 15 ms to 25 ms

E 3 V 3 V > 140 ms > 30 ms

F 4.5 V 5 V 35 ms to 45 ms 10 ms to 20 ms

7.3.5.2.1 Waveform Sequencer

The waveform sequencer queues waveform identifiers for playback. Eight sequence registers queue up to eight

waveforms for sequential playback. A waveform identifier is an integer value referring to the index position of a

waveform in the ROM library. Playback begins at register address 0x04 when the user asserts the GO bit

(register 0x0C). When playback of that waveform ends, the waveform sequencer plays the waveform identifier

held in register 0x05 if the next waveform is non-zero. The waveform sequencer continues in this way until it

reaches an identifier value of zero or until all eight identifiers are played (register addresses 0x04 through 0x0B),

whichever scenario is reached first.

The waveform identifier range is 1 to 127. The MSB of each sequence register can implement a delay between

sequence waveforms. When the MSB is high, bits [6:0] indicate the length of the wait time. The wait time for that

step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

7.3.5.2.2 Library Parameterization

The ROM waveforms are augmented by the time offset registers (registers 0x0D to 0x10). The augmentation

occurs only for the ROM waveforms and not for the other interfaces (such as PWM and RTP). The purpose of

the functionality is to add time stretching (or time shrinking) to the waveform. This functionality is useful for

customizing the entire library of waveforms for a specific actuator rise time and fall time.

The time parameters that can be stretched or shrunk include:

ODT Overdrive time

SPT Sustain positive time

SNT Sustain Negative Time

BRT Brake Time

The time values are additive offsets and are 8-bit signed values. The default offset of the time values is 0.

Positive values add and negative values subtract from the time value of the effect that is currently played. The

most positive value in the waveform is automatically interpreted as the overdrive time, and the most negative

value in the waveform is automatically interpreted as the brake time. The time-offset parameters are applied to

both voltage-time pairs and linear ramps. For linear ramps, linear interpolation is stretched (or shrunk) over the

two operative points for the period (see Equation 3).

t + t

(ofs)

where

• t

(ofs)

is the time offset (3)

Changing the playback interval can also manipulate the waveforms stored in memory. Each waveform in memory

has a granularity of 5 ms. If the user desires greater granularity, a 1-ms playback interval can be obtained by

asserting the PLAYBACK_INTERVAL bit in register 0x1F.

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