"DVI信号转换器功能比较分析：TFP401 vs THS8200"

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7 Specifications

7.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

, AV

, PV

Supply voltage –0.3 4 V

Input voltage range, logic/analog signals –0.3 4 V

Operating ambient temperature 0 70 °C

Package power dissipation/PowerPAD

package

Soldered

(2)

4.3

Not soldered

(3)

2.7

JEDEC latchup (EIA/JESD78) 100 mA

stg

Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Specified with PowerPAD bond pad on the backside of the package soldered to a 2-oz. (0.071-mm thick) Cu plate PCB thermal plane.

Specified at maximum allowed operating temperature, 70°C.

(3) PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating

temperature, 70°C.

7.2 ESD Ratings

VALUE UNIT

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2500

Charged-device model (CDM), per JEDEC specification JESD22-

C101

(2)

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT

(DV

, AV

, PV

, OV

) Supply voltage 3 3.3 3.6 V

pix

(1)

Pixel time 6.06 40 ns

Single-ended analog-input termination resistance 45 50 55 Ω

Operating free-air temperature 0 25 70 °C

(1) t

pix

is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to tpix when in

1-pixel/clock mode and 2t

pix

when in 2-pixel/clock mode.

7.4 Thermal Information

THERMAL METRIC

(1)

TFP401, TFP401A

UNITPZP (HTQFP)

100 PINS

θJA

Junction-to-ambient thermal resistance 26

°C/W

θJC(top)

Junction-to-case (top) thermal resistance 12.3

θJB

Junction-to-board thermal resistance 7.3

Junction-to-top characterization parameter 0.3

Junction-to-board characterization parameter 7.2

θJC(bot)

Junction-to-case (bottom) thermal resistance 1.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TFP401, TFP401A

SLDS120H – MARCH 2000 – REVISED MARCH 2022

www.ti.com

6 Submit Document Feedback

Product Folder Links: TFP401 TFP401A

7.5 DC Digital I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level digital input voltage

(1)

2 DV

Low-level digital input voltage

(1)

0 0.8 V

High-level output drive current

(2)

ST = high, V

= 2.4 V 5 10 14

ST = low, V

= 2.4 V 3 6 9

Low-level output drive current

(2)

ST = high, V

= 0.8 V 10 13 19

ST = low, V

= 0.8 V 5 7 11

Hi-Z output leakage current PD = low or PDO = low –1 1 μA

(1) Digital inputs are labeled DI in I/O column of Terminal Functions table.

(2) Digital outputs are labeled DO in I/O column of Terminal Functions table.

7.6 DC Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Analog input differential voltage

(1)

75 1200 mV

Analog input common-mode voltage

(1)

– 300 AV

– 37 mV

I(OC)

Open-circuit analog input voltage AV

– 10 AV

+ 10 mV

DD(2PIX)

Normal 2-pix/clock power supply current

(2)

ODCK = 82.5 MHz, 2-pix/clock 370 mA

Power-down current

(3)

PD = low 10 mA

PDO

Output drive power-down current

(3)

PDO = low 35 mA

(1) Specified as dc characteristic with no overshoot or undershoot.

(2) Alternating 2-pixel black/2-pixel white pattern. ST = high, STAG = high, QE[23:0] and QO[23:0] C

= 10 pF.

(3) Analog inputs are open circuit (transmitter is disconnected from TFP401/401A).

7.7 AC Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ID(2)

Differential input sensitivity

(1)

150 1560 mV

p-p

Analog input intra-pair (+ to –) differential skew

(8)

0.4 t

bit

(2)

ccs

Analog input inter-pair or channel-to-channel

skew

(8)

1 t

pix

(3)

ijit

Worst-case differential input clock jitter tolerance

(8)

(4)

50 ps

Fall time of data and control signals

(5)

(6)

ST = low, C

= 5 pF 2.4

ST = high, C

= 10 pF 1.9

Rise time of data and control signals

(5)

(6)

ST = low, C

= 5 pF 2.4

ST = high, C

= 10 pF 1.9

Rise time of ODCK clock

(5)

ST = low, C

= 5 pF 2.4

ST = high, C

= 10 pF 1.9

Fall time of ODCK clock

(5)

ST = low, C

= 5 pF 2.4

ST = high, C

= 10 pF 1.9

su1

Setup time, data and control signal to falling edge of ODCK

1 pixel/clock, PIXS = low, OCK_INV =

low

1.8

2 pixel/clock, PIXS = high,

STAG = high, OCK_INV = low

3.8

2 pixel and STAG, PIXS = high, STAG =

low, OCK_INV = low

0.7

www.ti.com

TFP401, TFP401A

SLDS120H – MARCH 2000 – REVISED MARCH 2022

Submit Document Feedback

Product Folder Links: TFP401 TFP401A

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