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首页ez-usb单片机寄存器手册详解
ez-usb单片机寄存器手册
ez-usb单片机寄存器手册是Cypress Semiconductor Corporation发布的一份技术参考手册,旨在为开发者提供ez-usb单片机的寄存器信息。该手册详细介绍了ez-usb单片机的各种寄存器的内容,是相关开发者必不可少的资料。
ez-usb单片机寄存器手册的主要内容包括:
1. ez-usb单片机寄存器架构:该部分介绍了ez-usb单片机的寄存器架构,包括寄存器的地址空间、寄存器的类型、寄存器的访问方式等。
2. ez-usb单片机寄存器列表:该部分列出了ez-usb单片机的所有寄存器,包括寄存器的名称、地址、类型、描述等信息。
3. ez-usb单片机寄存器操作:该部分介绍了ez-usb单片机寄存器的操作,包括寄存器的读写操作、寄存器的访问限制等。
4. ez-usb单片机寄存器应用:该部分介绍了ez-usb单片机寄存器在实际应用中的使用,包括数据传输、串口通信、I/O操作等。
ez-usb单片机寄存器手册对于开发者来说非常重要,因为它提供了详细的寄存器信息,可以帮助开发者更好地理解和使用ez-usb单片机。此外,该手册还提供了Cypress Semiconductor Corporation的免责声明和版权信息。
ez-usb单片机寄存器手册的特点包括:
* 详细的寄存器信息:该手册提供了详细的ez-usb单片机寄存器信息,包括寄存器的地址空间、类型、描述等信息。
* 实用的应用示例:该手册提供了ez-usb单片机寄存器在实际应用中的使用示例,包括数据传输、串口通信、I/O操作等。
* 权威的来源:该手册是Cypress Semiconductor Corporation官方发布的技术参考手册,具有很高的权威性和可靠性。
ez-usb单片机寄存器手册是开发者不可或缺的参考资料,对于ez-usb单片机的开发和应用具有很高的参考价值。
xvi List of Figures
(List of Figures)
Figure 10-30. FIFO-Read w/ AUTOIN = 0, Committing Packets via INPKTEND w/SKIP=0 ..............10-47
Figure 10-31. FIFO-Read w/ AUTOIN = 0, Committing Packets via EPxBCL ....................................10-48
Figure 10-32. AUTOIN=1, GPIF FIFO Read Transactions, AUTOIN = 1 ...........................................10-48
Figure 10-33. FIFO-Read Transaction Code, AUTOIN = 1 ................................................................10-49
Figure 10-34. Firmware intervention, AUTOIN = 0/1 ..........................................................................10-49
Figure 10-35. Committing a Packet by Writing INPKTEND with EPx Number (w/SKIP=0) ................10-50
Figure 10-36. Skipping a Packet by Writing to INPKTEND w/SKIP=1 ...............................................10-50
Figure 10-37. Sourcing an IN Packet by writing to EPxBCH:L ...........................................................10-51
Figure 10-38. Firmware Launches a FIFO-Write Waveform ..............................................................10-52
Figure 10-39. Example FIFO-Write Transaction .................................................................................10-52
Figure 10-40. FIFO-Write Transaction Waveform ..............................................................................10-53
Figure 10-41. GPIFTool Setup for the Waveform of Figure 10-40 .....................................................10-53
Figure 10-42. FIFO-Write Transaction Functions ...............................................................................10-54
Figure 10-43. Initialization Code for FIFO-Write Transactions ...........................................................10-55
Figure 10-44. FIFO-Write w/ AUTOOUT = 0, Committing Packets via EPxBCL ................................10-55
Figure 10-45. CPU not in data path, AUTOOUT=1 ............................................................................10-56
Figure 10-46. TD_Init Example: Configuring AUTOOUT = 1 .............................................................10-56
Figure 10-47. FIFO-Write Transaction Code, AUTOOUT = 1 ............................................................10-56
Figure 10-48. Firmware can Skip or Commit, AUTOOUT = 0 ............................................................10-57
Figure 10-49. Initialization Code for AUTOOUT = 0 ...........................................................................10-57
Figure 10-50. Committing an OUT Packet by Writing OUTPKTEND w/SKIP=0 ................................10-57
Figure 10-51. Skipping an OUT Packet by Writing OUTPKTEND w/SKIP=1 .....................................10-58
Figure 10-52. Sourcing an OUT Packet (AUTOOUT = 0) ..................................................................10-58
Figure 10-53. Ensuring that the FIFO is Clear after Power-On-Reset ................................................10-59
Figure 10-54. Burst FIFO-Read Transaction Functions .....................................................................10-60
Figure 10-55. Initialization for Burst FIFO-Read Transactions ...........................................................10-61
Figure 10-56. Burst FIFO-Read Transaction Example, Writing INPKTEND w/SKIP=0 to Commit ....10-62
Figure 10-57. Burst FIFO-Read Transaction Example, Writing EPxBCL to Commit ..........................10-63
Figure 11-1. FX2 CPU Features .........................................................................................................11-1
Figure 11-2. FX2 to Standard 8051 Timing Comparison ....................................................................11-4
Figure 11-1. FX2 Internal Data RAM ..................................................................................................11-7
Figure 13-1. FX2 I/O Pin ....................................................................................................................13-2
Figure 13-2. I/O Port Output-Enable Registers ..................................................................................13-3
Figure 13-3. I/O Port Data Registers ..................................................................................................13-4
Figure 13-4. I/O-Pin Logic when Alternate Function is an OUTPUT ..................................................13-5
Figure 13-5. I/O-Pin Logic when Alternate Function is an INPUT ......................................................13-6
Figure 13-6. General I²C Transfer ....................................................................................................13-12
Figure 13-7. Addressing an I²C Peripheral .......................................................................................13-13
Figure 13-8. I²C-Compatible Registers .............................................................................................13-14
Figure 14-1. Timer 0/1 - Modes 0 and 1 .............................................................................................14-3
List of Figures xvii
(List of Figures)
Figure 14-2. Timer 0/1 - Mode 2 .........................................................................................................14-6
Figure 14-3. Timer 0 - Mode 3 ............................................................................................................14-7
Figure 14-4. Timer 2 - Timer/Counter with Capture ..........................................................................14-10
Figure 14-5. Timer 2 - Timer/Counter with Auto Reload ...................................................................14-11
Figure 14-6. Timer 2 - Baud Rate Generator Mode ..........................................................................14-12
Figure 14-7. Serial Port Mode 0 Receive Timing - Low Speed Operation ........................................14-18
Figure 14-8. Serial Port Mode 0 Receive Timing - High Speed Operation .......................................14-18
Figure 14-9. Serial Port Mode 0 Transmit Timing - Low Speed Operation .......................................14-19
Figure 14-10. Serial Port Mode 0 Transmit Timing - High Speed Operation ......................................14-19
Figure 14-11. Serial Port 0 Mode 1 Transmit Timing ..........................................................................14-23
Figure 14-12. Serial Port 0 Mode 1 Receive Timing ...........................................................................14-24
Figure 14-13. Serial Port 0 Mode 2 Transmit Timing ..........................................................................14-25
Figure 14-14. Serial Port 0 Mode 2 Receive Timing ...........................................................................14-26
Figure 14-15. Serial Port 0 Mode 3 Transmit Timing ..........................................................................14-27
Figure 14-16. Serial Port 0 Mode 3 Receive Timing ...........................................................................14-27
Figure 15-1. Register Description Format ..........................................................................................15-2
Figure 15-2. Single Instruction to Read Port B ...................................................................................15-4
Figure 15-3. Single Instruction to Write to Port C ...............................................................................15-4
Figure 15-4. Use Bit 2 to set PORTD - Single Instruction ..................................................................15-9
Figure 15-5. Use OR to Set Bit 3 ........................................................................................................15-9
Figure 15-6. GPIF Waveform Descriptor Data .................................................................................15-13
Figure 15-7. CPU Control and Status ...............................................................................................15-13
Figure 15-8. Interface Configuration (Ports, GPIF, slave FIFOs) .....................................................15-14
Figure 15-9. IFCLK Configuration .....................................................................................................15-15
Figure 15-10. Slave FIFO FLAGA-FLAGD Pin Configuration ............................................................15-18
Figure 15-11. Restore FIFOs to Reset State ......................................................................................15-20
Figure 15-12. Breakpoint Control .......................................................................................................15-20
Figure 15-13. Breakpoint Address High .............................................................................................15-21
Figure 15-14. Breakpoint Address Low ..............................................................................................15-21
Figure 15-15. 230 Kbaud Internally Generated Reference Clock .......................................................15-22
Figure 15-16. Slave FIFO Interface Pins Polarity ...............................................................................15-22
Figure 15-17. Chip Revision ID ..........................................................................................................15-23
Figure 15-18. Chip Revision Control ..................................................................................................15-24
Figure 15-19. Endpoint 1-OUT/Endpoint 1-IN Configurations ............................................................15-26
Figure 15-20. Endpoint 2 Configuration ..............................................................................................15-27
Figure 15-21. Endpoint 4 Configuration ..............................................................................................15-27
Figure 15-22. Endpoint 6 Configuration ..............................................................................................15-27
Figure 15-23. Endpoint 8 Configuration ..............................................................................................15-27
Figure 15-24. Endpoint 2, 4, 6 and 8 /Slave FIFO Configuration .......................................................15-29
Figure 15-25. Endpoint 2 and 6 AUTOIN Packet Length High ...........................................................15-31
xviii List of Figures
(List of Figures)
Figure 15-26. Endpoint 4 and 8 AUTOIN Packet Length High ...........................................................15-31
Figure 15-27. Endpoint 2, 4, 6, 8 AUTOIN Packet Length Low ..........................................................15-32
Figure 15-28. Endpoint 2/Slave FIFO Programmable Flag High ........................................................15-33
Figure 15-29. Endpoint 6/Slave FIFO Programmable Flag High ........................................................15-34
Figure 15-30. Endpoint 4/Slave FIFO Programmable Flag High ........................................................15-36
Figure 15-31. Endpoint 8/Slave FIFO Programmable Flag High ........................................................15-37
Figure 15-32. Endpoint 2, 4, 6, 8/Slave FIFO Programmable Flag Low .............................................15-38
Figure 15-33. Maximum FIFO Sizes ..................................................................................................15-40
Figure 15-34. Endpoint ISO IN Packets per Frame ............................................................................15-41
Figure 15-35. Force IN Packet End ....................................................................................................15-41
Figure 15-36. Force OUT Packet End ................................................................................................15-42
Figure 15-37. Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Enable ..................................................15-43
Figure 15-38. Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Request ................................................15-44
Figure 15-39. IN-BULK-NAK Interrupt Enable ....................................................................................15-45
Figure 15-40. IN-BULK-NAK Interrupt Request .................................................................................15-45
Figure 15-41. Endpoint Ping-NAK/IBN Interrupt Enable ....................................................................15-46
Figure 15-42. Endpoint Ping-NAK/IBN Interrupt Request ..................................................................15-46
Figure 15-43. USB Interrupt Enables .................................................................................................15-47
Figure 15-44. USB Interrupt Requests ...............................................................................................15-47
Figure 15-45. Endpoint Interrupt Enables ..........................................................................................15-49
Figure 15-46. Endpoint Interrupt Requests ........................................................................................15-49
Figure 15-47. GPIF Interrupt Enable ..................................................................................................15-50
Figure 15-48. GPIF Interrupt Request ................................................................................................15-50
Figure 15-49. USB Error Interrupt Enables ........................................................................................15-51
Figure 15-50. USB Error Interrupt Request ........................................................................................15-51
Figure 15-51. USB Error Counter and Limit .......................................................................................15-52
Figure 15-52. Clear Error Count EC3:0 ..............................................................................................15-52
Figure 15-53. INT 2 (USB) Autovector ...............................................................................................15-53
Figure 15-54. INT 4 (slave FIFOs & GPIF) Autovector .......................................................................15-53
Figure 15-55. INT 2 and INT 4 Setup .................................................................................................15-54
Figure 15-56. I/O PORTA Alternate Configuration .............................................................................15-55
Figure 15-57. I/O PORTC Alternate Configuration .............................................................................15-56
Figure 15-58. I/O PORTE Alternate Configuration .............................................................................15-56
Figure 15-59. I²C-Compatible Bus Control and Status .......................................................................15-57
Figure 15-60. I²C-Compatible Bus Data .............................................................................................15-59
Figure 15-61. I²C-Compatible Bus Control .........................................................................................15-59
Figure 15-62. AUTOPTR1 & AUTOPTR2 MOVX access (when APTREN=1) ...................................15-60
Figure 15-63. USB Control and Status ...............................................................................................15-63
Figure 15-64. Enter Suspend State ....................................................................................................15-64
Figure 15-65. Wakeup Control & Status .............................................................................................15-64
List of Figures xix
(List of Figures)
Figure 15-66. Data Toggle Control .....................................................................................................15-65
Figure 15-67. USB Frame Count HIGH ..............................................................................................15-66
Figure 15-68. USB Frame Count Low ................................................................................................15-67
Figure 15-69. USB Microframe Count ................................................................................................15-67
Figure 15-70. USB Function Address .................................................................................................15-68
Figure 15-71. Endpoint 0 (Byte Count High) ......................................................................................15-68
Figure 15-72. Endpoint 0 Control and Status (Byte Count Low) ........................................................15-69
Figure 15-73. Endpoint 1 OUT/IN Byte Count ....................................................................................15-69
Figure 15-74. Endpoint 2 and 6 Byte Count High ...............................................................................15-70
Figure 15-75. Endpoint 4 and 5 Byte Count High ...............................................................................15-70
Figure 15-76. Endpoint 2, 4, 6, 8 Byte Count Low ..............................................................................15-71
Figure 15-77. Endpoint 0 Control and Status .....................................................................................15-71
Figure 15-78. Endpoint 1 OUT/IN Control and Status ........................................................................15-72
Figure 15-79. Endpoint 2 Control and Status .....................................................................................15-74
Figure 15-80. Endpoint 4 Control and Status .....................................................................................15-74
Figure 15-81. Endpoint 6 Control and Status .....................................................................................15-75
Figure 15-82. Endpoint 8 Control and Status .....................................................................................15-76
Figure 15-83. Endpoint 2 and 4 Slave FIFO Flags .............................................................................15-77
Figure 15-84. Endpoint 6 and 8 Slave FIFO Flags .............................................................................15-77
Figure 15-85. Endpoint 2 Slave FIFO Total Byte Count High .............................................................15-78
Figure 15-86. Endpoint 6 Slave FIFO Total Byte Count High .............................................................15-78
Figure 15-87. Endpoint 4 and 8 Slave FIFO Byte Count High ............................................................15-79
Figure 15-88. Endpoint 2, 4, 6, 8 Slave FIFO Byte Count Low ..........................................................15-79
Figure 15-89. Setup Data Pointer High Address Byte ........................................................................15-80
Figure 15-90. Setup Data Pointer Low Address Byte .........................................................................15-80
Figure 15-91. Setup Data Pointer AUTO Mode ..................................................................................15-81
Figure 15-92. Setup Data - 8 Bytes ....................................................................................................15-82
Figure 15-93. GPIF Waveform Selector .............................................................................................15-83
Figure 15-94. GPIF Done and Idle Drive ............................................................................................15-83
Figure 15-95. CTL Output States in Idle .............................................................................................15-84
Figure 15-96. CTL Output Drive Type ................................................................................................15-84
Figure 15-97. GPIF Address High ......................................................................................................15-86
Figure 15-98. GPIF Address Low .......................................................................................................15-87
Figure 15-99. GPIF Transaction Count Byte3 ....................................................................................15-95
Figure 15-100. GPIF Transaction Count Byte2 ....................................................................................15-95
Figure 15-101. GPIF Transaction Count Byte1 ....................................................................................15-96
Figure 15-102. GPIF Transaction Count Byte0 ....................................................................................15-96
Figure 15-103. Endpoint 2, 4, 6, 8 GPIF Flag Select ............................................................................15-97
Figure 15-104. Endpoint 2, 4, 6, and 8 GPIF Stop Transaction ...........................................................15-98
Figure 15-105. Endpoint 2, 4, 6, and 8 Slave FIFO GPIF Trigger ........................................................15-98
xx List of Figures
(List of Figures)
Figure 15-106. GPIF Data High (16-Bit Mode) .....................................................................................15-99
Figure 15-107. Read/Write GPIF Data LOW & Trigger Transaction ....................................................15-99
Figure 15-108. Read GPIF Data LOW, No Transaction Trigger .........................................................15-100
Figure 15-109. GPIF Ready Pins .......................................................................................................15-100
Figure 15-110. GPIF Ready Status Pins ............................................................................................15-101
Figure 15-111. Abort GPIF .................................................................................................................15-101
Figure 15-112. EP0 IN/OUT Buffer ....................................................................................................15-102
Figure 15-113. EP1-OUT Buffer .........................................................................................................15-102
Figure 15-114. EP1-IN Buffer .............................................................................................................15-103
Figure 15-115. 512/1024-byte EP2/Slave FIFO Buffer ......................................................................15-103
Figure 15-116. 512-byte EP4/Slave FIFO Buffer ...............................................................................15-104
Figure 15-117. 512/1024-byte EP6/Slave FIFO Buffer ......................................................................15-104
Figure 15-118. 512-byte EP8/Slave FIFO Buffer ...............................................................................15-105
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