EZ-USB 技术参考手册：USB GPIF/Slave FIFO 开发

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"USB GPIF/Slave FIFO 开发技术手册" 该手册是 Cypress Semiconductor 出版的 EZ-USB 技术参考手册，文档编号 001-13670 Rev.*D，主要涵盖了 USB General-Purpose Input/Output (GPIF) 和 Slave FIFO 的开发技术。USB GPIF 是一种接口协议，它允许微控制器或应用处理器通过 USB 接口与外部设备进行高速数据传输。Slave FIFO 则是作为 USB 主设备与从设备间数据交换的一种存储单元，确保数据传输的同步和高效。手册可能包括以下关键知识点： 1. **EZ-USB 系列芯片介绍**：EZ-USB 系列是 Cypress Semiconductor 提供的 USB 解决方案，它集成了 USB 控制器和接口逻辑，方便开发者快速实现 USB 功能。 2. **USB GPIF 协议**：详细解释了 GPIF 的工作原理、配置选项和时序，包括如何设置 GPIF 的输入输出模式，以及如何处理数据传输的握手信号。 3. **Slave FIFO 设计**：阐述了 Slave FIFO 的结构、功能，以及如何配置和优化其性能，以实现高带宽的数据传输。 4. **硬件设计指南**：提供了与 EZ-USB 芯片连接的硬件设计指导，包括GPIO配置、时钟管理、电源需求等。 5. **软件开发支持**：涵盖与 GPIF 和 Slave FIFO 配合使用的固件和驱动程序开发，可能包括示例代码和API接口说明。 6. **兼容性和标准遵循**：讨论了如何确保系统符合 USB 规范，以及与其他标准（如 I2C）的兼容性。购买 I2C 组件时，手册可能会提及 Philips I2C Patent Rights 的许可条款。 7. **故障排查和调试工具**：可能包含了一些用于检测和解决 USB GPIF 及 Slave FIFO 问题的工具和技术。 8. **安全性和可靠性**：可能涉及了在实际应用中如何保证数据传输的安全性和系统的稳定性。由于手册是英文版，建议配合中文资料一起阅读，以确保对所有内容有清晰的理解。此外，Cypress Semiconductor 的官方网站（http://www.cypress.com）可能提供更多的支持资源，包括更新的手册、软件下载和开发者论坛，这些都是深入学习和解决问题的重要途径。

16 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *D

Introducing EZ-USB®

1.7.1 Bulk Transfers

Figure 1-2. Two Bulk Transfers, IN and OUT

Bulk data is ‘bursty,’ traveling in packets of 8, 16, 32, or 64

bytes at full speed or 512 bytes at high speed. Bulk data has

guaranteed accuracy, due to an automatic retry mechanism

for erroneous data. The host schedules bulk packets when

there is available bus time. Bulk transfers are typically used

for printer, scanner, or modem data. Bulk data has built-in

flow control provided by handshake packets.

1.7.2 Interrupt Transfers

Figure 1-3. An Interrupt Transfer

Interrupt data is like bulk data; it can have packet sizes of 1

through 64 bytes at full speed or up to 1024 bytes at high-

speed. Interrupt endpoints have an associated polling inter-

val that ensures they will be polled (receive an IN token) by

the host on a regular basis.

1.7.3 Isochronous Transfers

Figure 1-4. An Isochronous Transfer

Isochronous data is time-critical and used to stream data like

audio and video. An isochronous packet may contain up to

1023 bytes at full speed, or up to 1024 bytes at high speed.

Time of delivery is the most important requirement for isoch-

ronous data. In every USB frame, a certain amount of USB

bandwidth is allocated to isochronous transfers. To lighten

the overhead, isochronous transfers have no handshake

(ACK/NAK/STALL/NYET), and no retries; error detection is

limited to a 16 bit CRC.

Isochronous transfers do not use the data-toggle mecha-

nism. Full-speed isochronous data uses only the DATA0

PID; high-speed isochronous data uses DATA0, DATA1,

DATA2 and MDATA.

In full-speed mode, only one isochronous packet can be

transferred per endpoint, per frame. In high-speed mode, up

to three isochronous packets can be transferred per end-

point, per microframe. For more details, refer to the Isochro-

nous Transfers discussion in Chapter 5 of the USB

specification.

1.7.4 Control Transfers

Figure 1-5. A Control Transfer

Control transfers configure and send commands to a device.

Because they are so important, they employ the most exten-

sive USB error checking. The host reserves a portion of

each USB frame for Control transfers.

Control transfers consist of two or three stages. The SETUP

stage contains eight bytes of USB CONTROL data. An

optional DATA stage contains more data, if required. The

STATUS (or handshake) stage allows the device to indicate

successful completion of a CONTROL operation.

1.8 Enumeration

Your computer is ON. You plug in a USB device, and the

Windows™ cursor switches to an hourglass and then back

to a cursor. Magically, your device is connected and its Win-

dows driver is loaded. Anyone who has installed a sound

card into a PC and has had to configure countless jumpers,

drivers, and I/O / Interrupt / DMA settings knows that a USB

connection is miraculous. We’ve all heard about Plug and

Play, but USB delivers the real thing.

Token Packet

Payload

Data

Data Packet

Token Packet

Payload

Data

Data Packet

H/S Pkt H/S Pkt

Token Packet

Payload

Data

Data Packet

H/S Pkt

Token Packet

Payload

Data

Data Packet

Token Packet

8 bytes

Setup

Data

Data Packet

H/S Pkt

Token Packet

Payload

Data

Data Packet

H/S Pkt

Token Packet

Data Pkt

H/S Pkt

SETUP

Stage

DATA

Stage

(optional)

STATUS

Stage

EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *D 17

Introducing EZ-USB®

How does all this happen automatically? Inside every USB

device is a table of descriptors. This table is the sum total of

the device’s requirements and capabilities. When you plug

into USB, the host goes through a sign on sequence:

1. The host sends a Get Descriptor-Device request to

address zero (all USB devices must respond to address

zero when first attached).

2. The device responds to the request by sending ID data

back to the host to identify itself.

3. The host sends a Set Address request, which assigns a

unique address to the just-attached device so it may be

distinguished from the other devices connected to the

bus.

4. The host sends more Get Descriptor requests, asking for

additional device information. From this, it learns every-

thing else about the device: number of endpoints, power

requirements, required bus bandwidth, what driver to

load, etc.

This sign-on process is called ‘Enumeration’.

1.8.1 Full Speed/High Speed Detection

The USB Specification requires that high-speed (480 Mbits/

sec) devices must also be capable of enumerating at full-

speed (12 Mbps). In fact, all high-speed devices begin the

enumeration process in full-speed mode; devices switch to

high-speed operation only after the host and device have

agreed to operate at high speed. The high-speed negotia-

tion process occurs during USB reset, via the ‘Chirp’ proto-

col described in Chapter 7 of the USB Specification.

When connected to a full-speed host, the EZ-USB FX2LP

enumerates as a full-speed device. When connected to a

high-speed host, the EZ-USB FX2LP automatically switches

to high-speed mode. The EZ-USB FX1 always enumerates

as a full-speed device. Neither the EZ-USB FX2LP or the

EZ-USB FX1 support the low-speed mode (1.5 Mbps).

1.9 The Serial Interface Engine

Figure 1-6. What the SIE Does

Every USB device has a Serial Interface Engine (SIE) which

connects to the USB data lines (D+ and D-) and delivers

data to and from the USB device. Figure 1-6 illustrates the

SIE’s role: it decodes the packet PIDs, performs error

checking on the data using the transmitted CRC bits, and

delivers payload data to the USB device.

Bulk transfers are ‘asynchronous’, meaning that they

include a flow control mechanism using ACK and NAK

handshake PIDs. The SIE indicates busy to the host by

sending a NAK handshake packet. When the USB device

has successfully transferred the data, it commands the SIE

to send an ACK handshake packet, indicating success. If

the SIE encounters an error in the data, it automatically indi-

cates no response instead of supplying a handshake PID.

This instructs the host to retransmit the data at a later time.

Serial

Interface

Engine

(SIE)

D+

D-

USB

Transceiver

Token Packet

Payload

Data

Data Packet

Token Packet

Payload

Data

Data Packet

H/S Pkt

Payload

Data

Payload

Data

H/S Pkt

18 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *D

Introducing EZ-USB®

To send data to the host, the SIE accepts bytes and control

signals from the USB device, formats it for USB transfer, and

sends it over D+ and D-. Because USB uses a self-clocking

data format (NRZI), the SIE also inserts bits at appropriate

places in the bit stream to guarantee a certain number of

transitions in the serial data. This is called ‘bit stuffing,’ and

is handled automatically by the EZ-USB’s SIE.

One of the most important features of the EZ-USB family is

that its configuration is soft. Instead of requiring ROM or

other fixed memory, it contains internal program/data RAM

which can be loaded over the USB. This makes modifica-

tions, specification revisions, and updates a snap.

The EZ-USB’s ‘smart’ SIE performs much more than the

basic functions shown in Figure 1-6; it can perform a full

enumeration by itself, which allows the EZ-USB to connect

as a USB device and download code into its RAM while its

CPU is held in reset. This added SIE functionality is also

made available to the EZ-USB programmer, to make devel-

opment easier and save code and processing time.

1.10 ReNumeration™

Because the EZ-USB’s configuration is ‘soft’, one chip can

take on the identities of multiple distinct USB devices.

When first plugged into USB, the EZ-USB enumerates auto-

matically and downloads firmware and USB descriptor

tables over the USB cable. Next, the EZ-USB enumerates

again, this time as a device defined by the downloaded infor-

mation. This patented two-step process, called ReNumera-

tion™, happens instantly when the device is plugged in, with

no hint that the initial download step has occurred.

Alternately, EZ-USB can also load its firmware from an

external EEPROM.

The Enumeration and ReNumeration™ chapter on page 51

describes these processes in detail.

1.11 EZ-USB Architecture

Figure 1-7. EZ-USB 56-Pin Package Simplified Block Diagram

The EZ-USB packs all the intelligence required by a USB

peripheral interface into a compact integrated circuit. As

Figure 1-7 illustrates, an integrated USB transceiver con-

nects to the USB bus pins D+ and D-. A Serial Interface

Engine (SIE) decodes and encodes the serial data and per-

forms error correction, bit stuffing, and the other signaling-

level tasks required by USB. Ultimately, the SIE transfers

parallel data to and from the USB interface.

The EZ-USB FX2LP SIE operates at full-speed (12 Mbps)

and high-speed (480 Mbps) rates. The EZ-USB FX1 SIE

operates at the full-speed (12 Mbps) rate only. To accommo-

date the increased bandwidth of USB 2.0, the EZ-USB end-

point FIFOs and slave FIFOs (which interface to external

logic or processors) are unified to eliminate internal data

transfer times.

The CPU is an enhanced 8051 with fast execution time and

added features. It uses internal RAM for program and data

storage.

The role of the CPU in a typical EZ-USB-based USB periph-

eral is two fold:

■ It implements the high-level USB protocol by servicing

host requests over the control endpoint (endpoint zero)

■ It is available for general-purpose system use

The high-level USB protocol is not bandwidth-critical, so the

EZ-USB’s CPU is well-suited for handling host requests over

Serial

Interface

Engine

(SIE)

USB

Transceiver

D+

D-

USB

Connector

OUT

data

I/O Ports

USB

Interface

Slave

FIFOs

Program &

Data

RAM

EZ-USB

GPIF

8/16

CPU

(Enhanced

8051)

CTL RDY

EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *D 19

Introducing EZ-USB®

the control endpoint. However, the data rates offered by

USB are too high for the CPU to process the USB data

directly. For this reason, the CPU is not usually in the high-

bandwidth data path between endpoint FIFOs and the exter-

nal interface. Note Instead, the CPU simply configures the

interface, then ‘gets out of the way’ while the unified EZ-

USB FIFOs move the data directly between the USB and

the external interface.

The FIFOs can be controlled by an external master, which

either supplies a clock and clock-enable signals to operate

synchronously, or strobe signals to operate asynchronously.

Alternately, the FIFOs can be controlled by an internal EZ-

USB timing generator called the General Programmable

Interface (GPIF). The GPIF serves as an ‘internal’ master,

interfacing directly to the FIFOs and generating user-pro-

grammed control signals for the interface to external logic.

Additionally, the GPIF can be made to wait for external

events by sampling external signals on its RDY pins. The

GPIF runs much faster than the FIFO data rate to give good

programmable resolution for the timing signals. It can be

clocked from either the internal EZ-USB clock or an exter-

nally supplied clock.

The EZ-USB’s CPU is rich in features. Up to five I/O ports

are available, as well as two USARTs, three counter/timers,

and an extensive interrupt system. It runs at a clock rate of

up to 48 MHz and uses four clocks per instruction cycle

instead of the twelve required by a standard 8051.

The EZ-USB chip family uses an enhanced SIE/USB inter-

face which simplifies EZ-USB code by implementing much

of the USB protocol. In fact, the EZ-USB can function as a

full USB device even without firmware.

All EZ-USB family chips operate at 3.3V. This simplifies the

design of bus-powered USB devices, since the 5V power

available at the USB connector (which the USB Specifica-

tion allows to be as low as 4.4V) can drive a 3.3V regulator

to deliver clean, isolated power to the EZ-USB chip.

EZ-USB is available in a 128-pin package which brings out

the 8051 address bus, data bus, and control signals to allow

connection of external memory and/or memory-mapped I/O.

Figure 1-8 is a block diagram for this package; The

Memory chapter on page 71, gives full details of the exter-

nal-memory interface.

Figure 1-8. EZ-USB 128-Pin Package Simplified Block Diagram

Serial

Interface

Engine

(SIE)

USB

Transceiver

D+

D-

USB

Connector

OUT

data

USB

Interface

Slave

FIFOs

Program &

Data

RAM

EZ-USB

GPIF

8/16

CTL RDY

Data Bus

Off-Chip

Memory

I/O Ports

CPU

(Enhanced

8051)

20 EZ-USB® Technical Reference Manual, Document # 001-13670 Rev. *D

Introducing EZ-USB®

1.12 EZ-USB Feature Summary

The EZ-USB chips include the following features:

■ Low power consumption enabling bus-powered designs

■ For EZ-USB FX2LP, an on-chip 480 Mbps transceiver.

For EZ-USB FX1, an on-chip 12 Mbps transceiver. Both

devices contain a PLL and SIE—the entire USB physical

layer (PHY).

■ Double-, triple- and quad-buffered endpoint FIFOs

accommodate the 480 Mbps USB data rate

■ Built in, enhanced 8051 running at up to 48 MHz

❐ Fully featured: 256 bytes of register RAM, two

USARTs, three timers, two data pointers

❐ Fast: four clocks (83.3 ns at 48 MHz) per instruction

cycle

❐ SFR access to control registers (including I/O ports)

that require high speed

❐ USB-vectored interrupts for low ISR latency

❐ Used for USB housekeeping and control, not to

move high-speed data

■ ‘Soft’ operation—USB firmware can be downloaded over

USB, eliminating the need for hard coded memory

■ Four interface FIFOs that can be internally or externally

clocked. The endpoint and interface FIFOs are unified to

eliminate data transfer time between USB and external

logic.

■ General Programmable Interface (GPIF), a microcoded

state machine which serves as a timing master for a

glueless interface to the EZ-USB FIFOs

■ ECC Generation based on the SmartMedia™ standard

The EZ-USB family offers single-chip USB 2.0 peripheral

solutions. Unlike designs that use an external PHY, the EZ-

USB integrates everything on one chip, eliminating costly

high pin-count packages and the need to route high speed

signals between chips.

1.13 EZ-USB Integrated

Microprocessor

The EZ-USB’s CPU uses on-chip RAM as program and data

memory. The Memory chapter on page 71, describes the

various internal/external memory options.

The CPU communicates with the SIE using a set of registers

occupying on-chip RAM addresses 0xE500-0xE6FF. These

registers are grouped and described by function in individual

chapters of this reference manual and summarized in regis-

ter order. See chapter “Registers” on page 211.

The CPU has two duties. First, it participates in the protocol

defined in the Universal Serial Bus Specification Version

2.0, Chapter 9, USB Device Framework. Thanks to the EZ-

USB’s ‘smart’ SIE, the firmware associated with the USB

protocol is simplified, leaving code space and bandwidth

available for the CPU’s primary duty—to help implement

your device. On the device side, abundant input/output

resources are available, including I/O ports, USARTs, and

an I2C bus master controller. These resources are

described in the Input/Output chapter on page 181, and the

Timers/Counters and Serial Interface chapter on page 193.

It is important to recognize that the EZ-USB architecture is

such that the CPU sets up and controls data transfers, but it

normally does not participate in high bandwidth transfers. It

is not in the data path; instead, the large data FIFOs that

handle endpoint data connect directly to outside interfaces.

To make the interface versatile, a programmable timing gen-

erator (GPIF, General Programmable Interface) can create

user-programmed waveforms for high bandwidth transfers

between the internal FIFOs and external logic.

The EZ-USB chips add eight interrupt sources to the stan-

dard 8051 interrupt system:

■ INT2: USB Interrupt

■ INT3: I2C Bus Interrupt

■ INT4: FIFO/GPIF Interrupt

■ INT4: External Interrupt 4

■ INT5: External Interrupt 5

■ INT6: External Interrupt 6

■ USART1: USART1 Interrupt

■ WAKEUP: USB Resume Interrupt

The EZ-USB chips provide 27 individual USB-interrupt

sources which share the INT2 interrupt, and 14 individual

FIFO/GPIF-interrupt sources which share the INT4 interrupt.

To save the code and processing time which normally would

be required to identify an individual interrupt source, the EZ-

USB provides a second level of interrupt vectoring called

Autovectoring. Each INT2 and INT4 interrupt source has its

own autovector, so when an interrupt requires service, the

proper ISR (interrupt service routine) is automatically

invoked. The Interrupts chapter on page 59 describes the

EZ-USB interrupt system.

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