Verilog实现的带控制器CPU设计

module top(rst,clk,//r_wf,ld_R,LDA,LDB,sel_rf,sel_alu,bus,FZ,FC,reg_sel,reg_out,ALU_B,R_B,LDAR,
           //out_AR,LDIR,out_IR,LOAD,out_pc,LDPC,PC_B,  
              start,bus,reg_sel,reg_out,FZ,FC,out_AR,out_IR,out_pc);

//input rst,clk,r_wf,ld_R,LDA,LDB,ALU_B,R_B,LDAR,LDIR,LOAD,LDPC,PC_B;
input rst,clk,start;
inout reg[7:0] bus;
//input[1:0]sel_rf;
//input[3:0]sel_alu;
output reg[1:0]reg_sel;
output reg[7:0]reg_out;
output FC,FZ;
output[7:0]out_AR,out_IR,out_pc;
wire r_wf,ld_R,LDA,LDB,ALU_B,R_B,LDAR,LDIR,LOAD,LDPC,PC_B;
reg[1:0]sel_rf;
reg[3:0]sel_alu;


alu myalu(.clock(clk),.rst(rst),.ALU_B(ALU_B),.S(sel_alu),.LEA(LDA),.LEB(LDB),.bus(bus),.FZ(FZ),.FC(FC));
rf myrf(.rst(rst),.clk(clk),.r_w(r_wf),.ldR(ld_R),.bus(bus),.sel(sel_rf),.R_B(R_B));
AR myAR(.clk(clk),.rst(rst),.ldar(LDAR),.bus(bus),.out_addr(out_AR));
IR myIR(.clk(clk),.rst(rst),.bus(bus),.ldir(LDIR),.ir_out(out_IR));
pc mypc(.bus(bus),.load(LOAD),.out(out_pc),.clk(clk),.rst(rst),.ldpc(LDPC),.pc_b(PC_B));
ctrol myctrol(.clk(clk),.rst(rst),.start(start),.sel_alu(sel_alu),.ALU_B(ALU_B),.load_r1(LDA),.load_r2(LDB),
              .ld_R(ld_R),.w_R(r_wf),.sel_R(sel_rf),.R_B(R_B),.LDAR(LDAR),.LDIR(LDIR),.load_PC(LOAD),.LDPC(LDPC),
              .pc_b(PC_B),.mr(MR),.mw(MW),.IOin(IOin),.IOout(IOout),.IR(out_IR));
always@(posedge clk)
if(rst)
begin
bus<=8'bz;

reg_out <=8'b0;
end
else
begin
reg_sel<=sel_rf;
reg_out<=bus;
end
endmodule




module ctrol(clk,rst,start,sel_alu,ALU_B,load_r1,load_r2,ld_R,w_R,sel_R,R_B,LDAR,LDIR,load_PC,LDPC,
             pc_b,mr,mw,IOin,IOout,IR);

input rst,start,clk;
input [7:0]IR;
output ALU_B,load_r1,load_r2,ld_R,w_R,R_B,LDAR,LDIR,load_PC,LDPC,pc_b,mr,mw,IOin,IOout;
output [3:0]sel_alu;
output [1:0]sel_R;

parameter s0=4'b0000,s1=4'b0001,s2=4'b0010,s3=4'b0011,s4=4'b0100,s5=4'b0101,
          s6=4'b0110,s7=4'b0111,s8=4'b1000,s9=4'b1001,s10=4'b1010,s1_1=4'b1011;

parameter IN= 8'b00100000,
      ADD=8'b00000000,
          OUT=8'b00110000,
          JMP=8'b11100000,
          HLT=9'b01010000;