Spartan-3E FPGA家族详解：数据表与功能介绍

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Spartan-3E FPGA Family Data Sheet (DS312 v3.8)详细介绍了Xilinx公司2009年8月发布的这一代FPGA器件的特性、架构概述、功能描述以及关键电气特性和工作条件。以下是主要内容的详细解读： 1. **介绍与订购信息**： - 该文档提供了Spartan-3E FPGA系列的入门指南，包括产品特性概述和订购须知。它可能包含了设计者需要了解的关键规格、产品系列定位以及如何选择适合应用需求的型号。 2. **功能描述**： - 功能模块详细列出了Spartan-3E FPGA的关键组成部分，如输入/输出块（IOBs），支持多种信号标准，如SelectIO。配置逻辑块（CLB）允许用户灵活布线逻辑，块内RAM用于存储数据，专用乘法器提供高性能计算能力。 - 内置的数字钟管理器（DCM）确保时钟系统的精确控制，而时钟网络设计则关乎系统性能和稳定性。此外，还涵盖了配置过程，包括配置数据的加载和保存，以及电源管理和生产步骤的说明。 3. **电气特性和工作条件**： - DCElectricalCharacteristics部分包含了器件的绝对最大操作参数，如供电电压范围、推荐的工作环境条件等。DC Characteristics关注静态工作时的性能，如电流、功耗等。SwitchingCharacteristics关注信号在电路中的传输速率和延迟，包括输入/输出引脚的时序规范、Slice（逻辑单元）的时序限制，以及DCMTiming（直流时序）的要求，这些都是设计和评估系统性能的关键因素。总结来说，这份Spartan-3E FPGA的数据表提供了设计师所需的所有技术细节，从基本的架构到实际应用中的性能参数，是进行硬件设计、评估系统兼容性以及优化FPGA配置的重要参考资料。在使用Spartan-3E系列FPGA时，必须仔细阅读并理解这些信息，以确保设计满足性能、功耗和可靠性的要求。

Functional Description

16 www.xilinx.com DS312-2 (v3.8) August 26, 2009

Product Specification

SelectIO Signal Standards

The Spartan-3E I/Os feature inputs and outputs that sup-

port a wide range of I/O signaling standards (Ta ble 6 and

Tabl e 7). The majority of the I/Os also can be used to form

differential pairs to support any of the differential signaling

standards (Ta ble 7).

To define the I/O signaling standard in a design, set the

IOSTANDARD attribute to the appropriate setting. Xilinx

provides a variety of different methods for applying the

IOSTANDARD for maximum flexibility. For a full description

of different methods of applying attributes to control

IOSTANDARD, refer to the Xilinx Software Manuals and

Help.

Spartan-3E FPGAs provide additional input flexibility by

allowing I/O standards to be mixed in different banks. For a

particular V

CCO

voltage, Tabl e 6 and Ta ble 7 list all of the

IOSTANDARDs that can be combined and if the IOSTAN-

DARD is supported as an input only or can be used for both

inputs and outputs.

Figure 10: Output DDR

OCLK1

From

Fabric

PAD

d+4d+3d+2d+1d

PAD

OCLK1

OCLK2

DS312-2_23_030105

d+1 d+3 d+5 d+7

d+2 d+4 d+6

d+8

d+9

d+8 d+10

d+5 d+6

d+7

Tabl e 6: Single-Ended IOSTANDARD Bank Compatibility

Single-Ended

IOSTANDARD

CCO

Supply/Compatibility Input Requirements

1.2V 1.5V 1.8V 2.5V 3.3V V

REF

Board

Termination

Voltage (V

)

LVTTL

- - - -

Input/

Output

N/R

(1)

N/R

LVCMOS 3 3

- - - -

Input/

Output

N/R N/R

LVCMOS 2 5

- - -

Input/

Output

Input N/R N/R

LVCMOS 1 8

- -

Input/

Output

Input Input N/R N/R

LVCMOS 1 5

Input/

Output

Input Input Input N/R N/R

LVCMOS 1 2

Input/

Output

Input Input Input Input

N/R

(1)

N/R

PCI33_3

- - - -

Input/

Output

N/R N/R

PCI66_3

- - - -

Input/

Output

N/R N/R

HSTL_I_18

- -

Input/

Output

Input Input 0.9 0.9

HSTL_III_18

- -

Input/

Output

Input Input 1.1 1.8

Functional Description

DS312-2 (v3.8) August 26, 2009 www.xilinx.com 17

Product Specification

HSTL and SSTL inputs use the Reference Voltage (V

REF

) to

bias the input-switching threshold. Once a configuration

data file is loaded into the FPGA that calls for the I/Os of a

given bank to use HSTL/SSTL, a few specifically reserved

I/O pins on the same bank automatically convert to V

REF

inputs. For banks that do not contain HSTL or SSTL, V

REF

pins remain available for user I/Os or input pins.

Differential standards employ a pair of signals, one the

opposite polarity of the other. The noise canceling proper-

ties (for example, Common-Mode Rejection) of these stan-

dards permit exceptionally high data transfer rates. This

subsection introduces the differential signaling capabilities

of Spartan-3E devices.

Each device-package combination designates specific I/O

pairs specially optimized to support differential standards. A

unique L-number, part of the pin name, identifies the

line-pairs associated with each bank (see Pinout Descrip-

tions in Module 4). For each pair, the letters P and N desig-

nate the true and inverted lines, respectively. For example,

the pin names IO_L43P_3 and IO_L43N_3 indicate the true

and inverted lines comprising the line pair L43 on Bank 3.

SSTL18_I

- -

Input/

Output

Input Input 0.9 0.9

SSTL2_I

- - -

Input/

Output

Input 1.25 1.25

Notes:

1. N/R - Not required for input operation.

Tabl e 6: Single-Ended IOSTANDARD Bank Compatibility (Continued)

Single-Ended

IOSTANDARD

CCO

Supply/Compatibility Input Requirements

1.2V 1.5V 1.8V 2.5V 3.3V V

REF

Board

Termination

Voltage (V

)

Tabl e 7: Differential IOSTANDARD Bank Compatibility

Differential

IOSTANDARD

CCO

Supply Input

Requirements:

REF

Differential Bank

Restriction

(1)

1.8V 2.5V 3.3V

LVDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

REF

is not used

for these I/O

standards

Applies to

Outputs Only

RSDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

Applies to

Outputs Only

MINI_LVDS_25 Input

Input,

On-chip Differential Termination,

Output

Input

Applies to

Outputs Only

LVPECL_25 Input Input Input

No Differential

Bank Restriction

(other I/O bank

restrictions might

apply)

BLVDS_25 Input

Input,

Output

Input

DIFF_HSTL_I_18

Input,

Output

Input Input

DIFF_HSTL_III_18

Input,

Output

Input Input

DIFF_SSTL18_I

Input,

Output

Input Input

DIFF_SSTL2_I Input

Input,

Output

Input

Notes:

1. Each bank can support any two of the following: LVDS_25 outputs, MINI_LVDS_25 outputs, RSDS_25 outputs.

Functional Description

18 www.xilinx.com DS312-2 (v3.8) August 26, 2009

Product Specification

CCO

provides current to the outputs and additionally pow-

ers the On-Chip Differential Termination. V

CCO

must be

2.5V when using the On-Chip Differential Termination. The

REF

lines are not required for differential operation.

To further understand how to combine multiple IOSTAN-

DARDs within a bank, refer to IOBs Organized into Banks,

page 19.

On-Chip Differential Termination

Spartan-3E devices provide an on-chip ~120Ω differential

termination across the input differential receiver terminals.

The on-chip input differential termination in Spartan-3E

devices potentially eliminates the external 100Ω termination

resistor commonly found in differential receiver circuits. Dif-

ferential termination is used for LVDS, mini-LVDS, and

RSDS as applications permit.

On-chip Differential Termination is available in banks with

CCO

= 2.5V and is not supported on dedicated input pins.

Set the DIFF_TERM attribute to TRUE to enable Differential

Termination on a differential I/O pin pair.

The DIFF_TERM attribute uses the following syntax in the

UCF file:

INST <I/O_BUFFER_INSTANTIATION_NAME>

DIFF_TERM = “<TRUE/FALSE>”;

Pull-Up and Pull-Down Resistors

Pull-up and pull-down resistors inside each IOB optionally

force a floating I/O or Input-only pin to a determined state.

Pull-up and pull-down resistors are commonly applied to

unused I/Os, inputs, and three-state outputs, but can be

used on any I/O or Input-only pin. The pull-up resistor con-

nects an IOB to V

CCO

through a resistor. The resistance

value depends on the V

CCO

voltage (see DC and Switch-

ing Characteristics in Module 3 for the specifications). The

pull-down resistor similarly connects an IOB to ground with

a resistor. The PULLUP and PULLDOWN attributes and

library primitives turn on these optional resistors.

By default, PULLDOWN resistors terminate all unused I/O

and Input-only pins. Unused I/O and Input-only pins can

alternatively be set to PULLUP or FLOAT. To change the

unused I/O Pad setting, set the Bitstream Generator (Bit-

Gen) option UnusedPin to PULLUP, PULLDOWN, or

FLOAT. The UnusedPin option is accessed through the

Properties for Generate Programming File in ISE. See Bit-

stream Generator (BitGen) Options.

During configuration a Low logic level on the HSWAP pin

activates pull-up resistors on all I/O and Input-only pins not

actively used in the selected configuration mode.

Keeper Circuit

Each I/O has an optional keeper circuit (see Figure 12) that

keeps bus lines from floating when not being actively driven.

The KEEPER circuit retains the last logic level on a line after

all drivers have been turned off. Apply the KEEPER

attribute or use the KEEPER library primitive to use the

KEEPER circuitry. Pull-up and pull-down resistors override

the KEEPER settings.

Slew Rate Control and Drive Strength

Each IOB has a slew-rate control that sets the output

switching edge-rate for LVCMOS and LVTTL outputs. The

SLEW attribute controls the slew rate and can either be set

to SLOW (default) or FAST.

Each LVCMOS and LVTTL output additionally supports up

to six different drive current strengths as shown in Ta bl e 8.

To adjust the drive strength for each output, the DRIVE

attribute is set to the desired drive strength: 2, 4, 6, 8, 12,

and 16. Unless otherwise specified in the FPGA application,

the software default IOSTANDARD is LVCMOS25, SLOW

slew rate, and 12 mA output drive.

Figure 11: Differential Inputs and Outputs

100Ω

~120Ω

Spartan-3E

Differential Input

= 50Ω

Spartan-3E

Differential

Output

Spartan-3E

Differential Input

with On-Chip

Differential

Terminator

= 50Ω

Spartan-3E

Differential

Output

DS312-2_24_082605

Figure 12: Keeper Circuit

Tabl e 8: Programmable Output Drive Current

IOSTANDARD

Output Drive Current (mA)

2 4 6 8 12 16

LVTTL



LVCMOS33 

Pull-up

Pull-down

Input Path

Output Path

Keeper

DS312-2_25_020807

Functional Description

DS312-2 (v3.8) August 26, 2009 www.xilinx.com 19

Product Specification

High output current drive strength and FAST output slew

rates generally result in fastest I/O performance. However,

these same settings generally also result in transmission

line effects on the printed circuit board (PCB) for all but the

shortest board traces. Each IOB has independent slew rate

and drive strength controls. Use the slowest slew rate and

lowest output drive current that meets the performance

requirements for the end application.

Likewise, due to lead inductance, a given package supports

a limited number of simultaneous switching outputs (SSOs)

when using fast, high-drive outputs. Only use fast,

high-drive outputs when required by the application.

IOBs Organized into Banks

The Spartan-3E architecture organizes IOBs into four I/O

banks as shown in Figure 13. Each bank maintains sepa-

rate V

CCO

and V

REF

supplies. The separate supplies allow

each bank to independently set V

CCO

. Similarly, the V

REF

supplies can be set for each bank. Refer to Ta ble 6 and

Tabl e 7 for V

CCO

and V

REF

requirements.

When working with Spartan-3E devices, most of the differ-

ential I/O standards are compatible and can be combined

within any given bank. Each bank can support any two of

the following differential standards: LVDS_25 outputs,

MINI_LVDS_25 outputs, and RSDS_25 outputs. As an

example, LVDS_25 outputs, RSDS_25 outputs, and any

other differential inputs while using on-chip differential ter-

mination are a valid combination. A combination not allowed

is a single bank with LVDS_25 outputs, RSDS_25 outputs,

and MINI_LVDS_25 outputs.

I/O Banking Rules

When assigning I/Os to banks, these V

CCO

rules must be

followed:

1. All V

CCO

pins on the FPGA must be connected even if a

bank is unused.

2. All V

CCO

lines associated within a bank must be set to

the same voltage level.

3. The V

CCO

levels used by all standards assigned to the

I/Os of any given bank must agree. The Xilinx

development software checks for this. Ta bl e 6 and

Tabl e 7 describe how different standards use the V

CCO

supply.

4. If a bank does not have any V

CCO

requirements,

connect V

CCO

to an available voltage, such as 2.5V or

3.3V. Some configuration modes might place additional

CCO

requirements. Refer to Configuration for more

information.

If any of the standards assigned to the Inputs of the bank

use V

REF

, then the following additional rules must be

observed:

1. All V

REF

pins must be connected within a bank.

2. All V

REF

lines associated with the bank must be set to

the same voltage level.

3. The V

REF

levels used by all standards assigned to the

Inputs of the bank must agree. The Xilinx development

software checks for this. Ta bl e 6 describes how different

standards use the V

REF

supply.

If V

REF

is not required to bias the input switching thresholds,

all associated V

REF

pins within the bank can be used as

user I/Os or input pins.

Package Footprint Compatibility

Sometimes, applications outgrow the logic capacity of a

specific Spartan-3E FPGA. Fortunately, the Spartan-3E

family is designed so that multiple part types are available in

pin-compatible package footprints, as described in Pinout

Descriptions in Module 4. In some cases, there are subtle

differences between devices available in the same footprint.

These differences are outlined for each package, such as

pins that are unconnected on one device but connected on

another in the same package or pins that are dedicated

inputs on one package but full I/O on another. When design-

ing the printed circuit board (PCB), plan for potential future

upgrades and package migration.

The Spartan-3E family is not pin-compatible with any previ-

ous Xilinx FPGA family.

Dedicated Inputs

Dedicated Inputs are IOBs used only as inputs. Pin names

designate a Dedicated Input if the name starts with IP, for

example, IP or IP_Lxxx_x. Dedicated inputs retain the full

functionality of the IOB for input functions with a single

LVCMOS25

 -

LVCMOS18

 - -

LVCMOS15

 - - -

LVCMOS12

 - - - - -

Figure 13: Spartan-3E I/O Banks (top view)

Tabl e 8: Programmable Output Drive Current

IOSTANDARD

Output Drive Current (mA)

2 4 6 8 12 16

DS312-2_26_021205

Bank 0

Bank 2

Bank 3

Bank 1

Functional Description

20 www.xilinx.com DS312-2 (v3.8) August 26, 2009

Product Specification

exception for differential inputs (IP_Lxxx_x). For the differ-

ential Dedicated Inputs, the on-chip differential termination

is not available. To replace the on-chip differential termina-

tion, choose a differential pair that supports outputs

(IO_Lxxx_x) or use an external 100Ω termination resistor on

the board.

ESD Protection

Clamp diodes protect all device pads against damage from

Electro-Static Discharge (ESD) as well as excessive voltage

transients. Each I/O has two clamp diodes: one diode

extends P-to-N from the pad to V

CCO

and a second diode

extends N-to-P from the pad to GND. During operation,

these diodes are normally biased in the off state. These

clamp diodes are always connected to the pad, regardless

of the signal standard selected. The presence of diodes lim-

its the ability of Spartan-3E I/Os to tolerate high signal volt-

ages. The V

absolute maximum rating in Tabl e 7 3 of DC

and Switching Characteristics (Module 3) specifies the

voltage range that I/Os can tolerate.

Supply Voltages for the IOBs

The IOBs are powered by three supplies:

1. The V

CCO

supplies, one for each of the FPGA’s I/O

banks, power the output drivers. The voltage on the

CCO

pins determines the voltage swing of the output

signal.

2. V

CCINT

is the main power supply for the FPGA’s internal

logic.

3. V

CCAUX

is an auxiliary source of power, primarily to

optimize the performance of various FPGA functions

such as I/O switching.

I/O and Input-Only Pin Behavior During

Power-On, Configuration, and User Mode

In this section, all behavior described for I/O pins also

applies to input-only pins and dual-purpose I/O pins that are

not actively involved in the currently-selected configuration

mode.

All I/O pins have ESD clamp diodes to their respective V

CCO

supply and from GND, as shown in Figure 5. The V

CCINT

(1.2V), V

CCAUX

(2.5V), and V

CCO

supplies can be applied in

any order. Before the FPGA can start its configuration pro-

cess, V

CCINT

, V

CCO

Bank 2, and V

CCAUX

must have reached

their respective minimum recommended operating levels

indicated in Table 7 4. At this time, all output drivers are in a

high-impedance state. V

CCO

Bank 2, V

CCINT

, and V

CCAUX

serve as inputs to the internal Power-On Reset circuit

(POR).

A Low level applied to the HSWAP input enables pull-up

resistors on user-I/O and input-only pins from power-on

throughout configuration. A High level on HSWAP disables

the pull-up resistors, allowing the I/Os to float. HSWAP con-

tains an internal pull-up resistor and defaults to High if left

floating. As soon as power is applied, the FPGA begins ini-

tializing its configuration memory. At the same time, the

FPGA internally asserts the Global Set-Reset (GSR), which

asynchronously resets all IOB storage elements to a default

Low state. Also see Pin Behavior During Configuration.

Upon the completion of initialization and the beginning of

configuration, INIT_B goes High, sampling the M0, M1, and

M2 inputs to determine the configuration mode. Configura-

tion data is then loaded into the FPGA. The I/O drivers

remain in a high-impedance state (with or without pull-up

resistors, as determined by the HSWAP input) throughout

configuration.

At the end of configuration, the GSR net is released, placing

the IOB registers in a Low state by default, unless the

loaded design reverses the polarity of their respective SR

inputs.

The Global Three State (GTS) net is released during

Start-Up, marking the end of configuration and the begin-

ning of design operation in the User mode. After the GTS

net is released, all user I/Os go active while all unused I/Os

are pulled down (PULLDOWN). The designer can control

how the unused I/Os are terminated after GTS is released

by setting the Bitstream Generator (BitGen) option Unused-

Pin to PULLUP, PULLDOWN, or FLOAT.

One clock cycle later (default), the Global Write Enable

(GWE) net is released allowing the RAM and registers to

change states. Once in User mode, any pull-up resistors

enabled by HSWAP revert to the user settings and HSWAP

is available as a general-purpose I/O. For more information

on PULLUP and PULLDOWN, see Pull-Up and Pull-Down

Resistors.

Behavior of Unused I/O Pins After

Configuration

By default, the Xilinx ISE development software automati-

cally configures all unused I/O pins as input pins with indi-

vidual internal pull-down resistors to GND.

This default behavior is controlled by the UnusedPin bit-

stream generator (BitGen) option, as described in Tabl e 6 9 .

JTAG Boundary-Scan Capability

All Spartan-3E IOBs support boundary-scan testing com-

patible with IEEE 1149.1/1532 standards. During bound-

ary-scan operations such as EXTEST and HIGHZ the

pull-down resistor is active. See JTAG Mode for more infor-

mation on programming via JTAG.

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