Cirrus Logic CS42L73: 超低功耗移动音频编解码器技术规格

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"音频编解码器CS42L73数据表" 《音频编解码器CS42L73：超低功耗移动音频与电话编解码器详解》 CS42L73是一款由Cirrus Logic公司推出的超低功耗移动音频和电话编解码器，其主要特性及应用范围如下： 1. **产品概述**： - **立体声模拟到数字转换器(ADC)**：CS42L73内置了立体声ADC，能够将模拟音频信号转换为数字信号，适用于音频录制或处理。 - **双模模拟或数字麦克风支持**：该编解码器可以支持两种类型的麦克风输入，适应不同应用场景。 - **双麦克风偏置发生器**：确保麦克风工作在正确的电压条件下，提供高质量的音频捕捉。 - **四个数字到模拟转换器(DACs)**：与五个输出端口相连，包括： - **地居中立体声耳机放大器**：提供清晰、无噪声的耳机播放体验。 - **地居中立体线性输出**：适用于连接其他音频设备。 - **单声道耳麦放大器**：针对耳机或耳塞式听筒设计。 - **单声道1-W扬声器放大器**：适合于手机或小型设备的扬声器播放。 - **单声道扬声器线路输出**：用于扩展立体声扬声器系统。 - **三个带有异步采样率转换器的串行端口**：允许灵活的数字音频接口，兼容多种采样率。 - **数字音频混合和路由**：支持音频流的混合和分配，提供高度自定义的音频处理功能。 2. **超低功耗**： - **3.8毫瓦的静默耳机回放功耗**：CS42L73在耳机播放模式下表现出极低的功耗，延长设备电池寿命。 3. **应用领域**： - **智能手机**：为现代智能手机提供高质量音频解决方案。 - **超便携式个人电脑**：提升超薄笔记本和二合一设备的音频性能。 - **移动互联网设备**：为平板电脑和其他移动互联网设备带来出色的音频体验。 4. **系统特性**： - **原生支持多种主时钟速率**：无需外部锁相环(PLL)，CS42L73能直接支持6/12/24MHz, 13/26MHz, 和19.2/38.4MHz的时钟频率，以及常见的音频采样率。 - **集成高效电源管理**：优化功耗，确保在保持音频质量的同时，减少能源消耗。 CS42L73的这些特点使其成为移动设备音频处理的理想选择，尤其在对电池续航有严格要求的智能设备中。其高效率、灵活性和卓越的音频性能，使得它能够满足各种复杂的音频应用场景，并且在不断发展的移动通信行业中保持竞争力。

16 DS882PP1

CS42L73

1.4 Digital Pin/Ball I/O Configurations

Notes:

• All outputs are disabled when RESET

is active.

• Internal weak pull up/down minimum and typical resistances are 550 k

 and 1 M

• Typical hysteresis is 500 mV within the 650 mV to 1.15 V window.

• The xSP_SCLK, xSP_LRCK, and xSP_SDOUT (x = X, A, or V) outputs may be disabled via register con-

trols as described in sections “High-impedance Mode” on page 50 and “Master and Slave Timing” on

page 51.

• Refer to specification table “Digital Interface Specifications and Characteristics” on page 41 for details

on the digital I/O DC characteristics (output voltages/load-capacity, input switching threshold voltages,

etc.). Inputs without integrated pull-ups/downs should not be left floating. All inputs must be driven or

pulled (internally and/or externally) to a valid High or Low level as defined in the specification table.

• Refer to specification tables “Switching Specifications - Serial Ports - I²S Format” on page 44 on

page 47, “Switching Specifications - Serial Ports - PCM Format” on page 45, and “Switching Specifica-

tions - Control Port” on page 46 for digital I/O AC characteristics (timing specifications).

• I/O voltage levels should not exceed the I/Os corresponding power supply voltage. I/O voltage levels

must not exceed the voltage listed table “Absolute Maximum Ratings” on page 20.

Power

Supply I/O Name Direction

Internal

Connections Configuration

VL MCLK1 Input Weak Pull-down Hysteresis on CMOS Input

MCLK2

Input Weak Pull-down

Hysteresis on CMOS Input

RESET

Input -

Hysteresis on CMOS Input

SCL Input - Hysteresis on CMOS Input

SDA

Input /

Output

Hysteresis on CMOS Input /

CMOS Open-drain Output

INT

Output Weak Pull-up CMOS Open-drain Output

XSP_SCLK

Input /

Output

Weak Pull-down

Hysteresis on CMOS Input /

CMOS Output

XSP_LRCK

Input /

Output

Weak Pull-down

Hysteresis on CMOS Input /

CMOS Output

XSP_SDIN Input Weak Pull-down Hysteresis on CMOS Input

XSP_SDOUT Output Weak Pull-down Tri-State-able CMOS Output

ASP_SCLK

Input /

Output

Weak Pull-down

Hysteresis on CMOS Input /

CMOS Output

ASP_LRCK

Input /

Output

Weak Pull-down

Hysteresis on CMOS Input /

CMOS Output

ASP_SDIN Input Weak Pull-down Hysteresis on CMOS Input

ASP_SDOUT Output Weak Pull-down Tri-State-able CMOS Output

VSP_SCLK

Input /

Output

Weak Pull-down

Hysteresis on CMOS Input /

CMOS Output

VSP_LRCK

Input /

Output

Weak Pull-down

Hysteresis on CMOS Input /

CMOS Output

VSP_SDIN Input Weak Pull-down Hysteresis on CMOS Input

VSP_SDOUT Output Weak Pull-down Tri-State-able CMOS Output

DMIC_SCLK Output - CMOS Output

DMIC_SD Input Weak Pull-down Hysteresis on CMOS Input

DS882PP1 17

CS42L73

2. TYPICAL CONNECTION DIAGRAM

Note 13

Optional

Bias Res.

Note 9

Note 4

DGND

SCL

SDA

ASP_LRCK

Applications

Processor

ASP_SCLK

ASP_SDIN

ASP_SDOUT

CS42L73

MIC2_BIAS

Line Level Out

Left & Right

SPKOUT+

SPKOUT-

MIC2

MIC2_REF

2.2 µF

SPK_VQ

AGND

2.2 µF

FILT+

EAROUT+

EAROUT-

VBAT

LINEINA

Line In

Left

100 k

LINEINB

Line In

Right

100 k

0.1 µF 4.7 µF

Note 2

2.2 µF

Note 1

+VCP_FILT

FLYC

FLYN

-VCP_FILT

2.2 µF

VCP

VANA

FLYP

2.2 µF

HPOUTB

HPOUTA

100 

33 nF

HPOUT_REF

LINEOUTB

LINEOUTA

LINEIN_REF

INA

VSP_LRCK

Baseband

Processor

MCLK1

VSP_SCLK

VSP_SDIN

VSP_SDOUT

2.2 µF

VD_FILT

1.0 µF

LINEO_REF

CPGND

INA

PGND

MIC1_BIAS

MIC1

MIC1_REF

ANA_VQ

4.7 µF

INT

RESET

INM

Note 7

1 µF

INM

Note 7

Note 8

Headphone Out

Left & Right

100 

33 nF

Speakerphone

(Left)

Ear Speaker

(Receiver)

Note 6

***

Note 5

I_P

3300 pF

562 

3300 pF

Note 10

Optional

LPF

Ground Ring

***

Note 4

Note 3

Key for Capacitor Types Required:

* Use low ESR, X7R/X5R capacitors

** Use low ESR, X7R/X5R capacitors, or,

if improved microphonic performance is

required, use tantalum capacitors with

equal or exceeding characteristics

*** Use NPO/C0G capacitors

*!* Use low ESR, X7R/X5R capacitors, or,

if de-rating factors reduce the effective

capacitance significantly, use tantalum

capacitors with equal or exceeding

characteristics

If no type symbol is shown next to a capacitor,

any type may be used.

Note, one should be mindful of ceramic

capacitor de-rating factors (e.g. percentage

the effective value reduced when d/c or small

a/c voltages are applied) when selecting

capacitor type, brand, and size.

0.1 µF

Note 11

Note 12

MCLK2

DMIC_SD

DMIC_SCLK

SPKLINEO+

SPKLINEO-

XSP_LRCK

XSP_SCLK

XSP_SDIN

XSP_SDOUT

MICB_FILT

Note 4

4.7 µF

*!*

BIAS

Note 9

Headset

Microphone

Handset

Microphone

Note 9

1 µF

Note 8

Note 6

BIAS

MIC2_SDET

Speakerphone

(Right)

L/R

DATA

L/R

DATA

Bluetooth

Transceiver

Cellular

Voice

AEC

Right/Data2

Digital

Microphone

Left/Data1

Digital

Microphone

VANA

0.1 µF

PMU

USB

+5 V

VBAT

LDO

Switching

Regulator

Reset

Generator

+1.8 V

VDIG

VBAT

Class-D

CS35L0x

*!*

Notes:

1. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown.

Larger capacitance reduces the ripple on the internal amplifiers’ supplies and in turn reduces the

amplifier’s distortion at high output power levels. Smaller capacitance may not sufficiently reduce ripple

to achieve the rated output power and distortion. Since the actual value of typical X7R/X5R ceramic

capacitors deviates from the nominal value by a percentage specified in the manufacturer’s data sheet,

capacitors should be selected based on the minimum output power and maximum distortion required.

2. The headphone amplifier’s output power and distortion are rated using the nominal capacitance shown

and using the default charge pump switching frequency. The required capacitance follows an inverse

relationship with the charge pump’s switching frequency. When increasing the switching frequency, the

capacitance may decrease; when lowering the switching frequency, the capacitance must increase.

Since the actual value of typical X7R/X5R ceramic capacitors deviates from the nominal value by a

percentage specified in the manufacturer’s data sheet, capacitors should be selected based on the

minimum output power, maximum distortion and maximum charge pump switching frequency required.

3. Lowering the capacitance below the value shown will affect PSRR, ADC-DAC isolation and

intermodulation, interchannel isolation and intermodulation and THD+N performance.

4. Additional bulk capacitance may be added to improve PSRR at low frequencies.

5. Series resistance in the path of the power supplies must be avoided. Any voltage drop on VCP will

directly impact the negative charge pump supply (-VHPFILT) and clip the audio output.

6. The value of R

BIAS

, a bias resistor used with electret condenser microphones, is dictated by the

microphone cartridge.

7. The reference terminal of the MICx inputs connects to the ground pin of the microphone cartridge. Gain

is applied only to the positive terminal.

8. The MICx_BIAS compensation capacitor must be 1 uF or greater. The capacitor’s ground terminal

should be connected to the same ground point as the MICx_REF ground connection.

9. Analog signal inputs (MICx & MICx_REF or LINEINx & LINEIN_REF) should be left floating if unused.

10. An optional passive Low Pass Filter (LPF) may be used to reduce quantization noise.

11. If tantalum capacitor use is desired, 2 tantalum capacitors of value 2x C

INM

, configured in series with

both anodes or both cathodes connected, must be used to avoid potentially damaging reverse voltages

across the tantalum capacitors.

12. If unused, tie MIC2_SDET to VP.

13. Optional Bias Resistors are used to minimize disturbances on the Line Inputs when their a/c coupling

capacitors are left floating and then reconnected to signal (e.g. when the Line Input signal comes from a

connector that isn’t always present). If the Line Input signal is always present, the Bias Resistors are

not required.

Figure 1. Typical Connection Diagram

Other Notes:

All external passive component values shown are

nominal values.

P_I

and R

values are defined in section “Digital

Interface Specifications and Characteristics” on

page 41.

For the spec. values listed in section “Character-

istic and Specifications” on page 19, a value of 1

F is used for C

INA

and a value of 0.1 F is used

for C

INM

As required, add protection circuitry to ensure

compliance with the Absolute Maximum Ratings

found on page 20.

18 DS882PP1

CS42L73

2.1 Low Profile Charge Pump Capacitors

From the “Typical Connection Diagram” on page 17 one sees that the recommended capacitor values for the charge

pump circuitry are all 2.2

F and the types are all X7R/X5R. Applications that require low profile versions of these

capacitors may use the following parts with a nominal height of only 0.5 mm:

Description: 2.2

F ±20%, 6.3 V, X5R, 0402, Height = 0.5 mm

Manufacturer, Part Number:

• KEMET, C0402C225M9PAC

2.2 Ceramic Capacitor Derating

The Typical Connection Diagram Capacitor Key highlights that ceramic capacitor derating factors can significantly

affect the in-circuit capacitance value and thus the performance of the CS42L73.

As is noted on the Typical Connection Diagram, the 4.7

F ceramic capacitors used for ANA_VQ or SPKR_VQ affect

low-frequency PSRR performance. Numerous types and brands of ceramic capacitors, under typical conditions, ex-

hibit effective capacitances well below their tolerance of ±20%, with some being de-rated by as much as -50%.

These same capacitors, when tested by a multimeter, read much closer to their rated value. A similar derating effect

has not been observed with tantalum capacitors.

The amount of derating observed varied with manufacturer and physical size; larger capacitors performed better as

did ones from Kemet Electronics Corp. and TDK Corp. of any size. This derating effect is described in datasheets

and applications notes from capacitor manufacturers. For instance, as DC and AC voltages are varied from the stan-

dard test points (applied DC and AC voltages for standard test points vs. PSRR test are 0 V and 1 V

RMS

@ 1 kHz

vs. 0.9 V and ~1 mV

RMS

@ 20 Hz to 20 kHz), it is documented that the capacitance varies significantly.

Based on these tests, the following ANA_VQ/SPKR_VQ capacitor parts are recommended for applications that re-

quire ceramic capacitors with the smallest PCB footprint:

Description: 4.7

F ±20%, 6.3V, X5R, 0603

Manufacturer, Part Number:

• KEMET, C0603C475M9PAC

• TDK, C1608X5R0J475M

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