TI DS90UB953A-Q1：4.16Gbps FPD-Link III serializer for automotive imaging sensors

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TI-DS90UB953A-Q1是一款专为FPD-Link III串行通信设计的高性能图像信号处理器（ISP）芯片，适用于对高速数据传输需求极高的应用场景，如2.3MP/60fps的全高清摄像头、雷达和各类传感器。该器件遵循严格的汽车电子委员会Q100（AEC-Q100，1级）标准，确保在极端环境温度下（-40°C至+125°C）稳定运行，并符合ISO10605和IEC61000-4-2ESD标准，保证了抗静电防护。 DS90UB953A-Q1支持PoC（Power over Coaxial Cable），即通过同轴电缆供电，这对于那些需要远程传输且无法通过传统电源线连接的设备非常有用。作为一款4.16Gbps级别的串行器，它能够处理高达832Mbps的数据通道，最多支持四个物理通道和四个虚拟通道，以满足多种传感器数据的高效传输。此器件强调精确的多摄像头同步，拥有灵活的可编程输出时钟发生器，能够适应不同摄像头的工作需求。它还提供了高级数据保护和诊断功能，例如CRC数据保护、传感器数据完整性检查、I2C写保护等，确保数据传输的安全性和准确性。温度和电压测量功能有助于监控设备工作状态，而可编程警报和线路故障检测则增加了系统的可靠性。此外，DS90UB953A-Q1支持单端同轴或屏蔽双绞线（STP）通信，适应了不同类型的传输介质。与DS90UB954-Q1或DS90UB960-Q1的串行/解串行器配合使用，可以构建完整的FPD-Link III通信链路，适用于各种需要高速、低延迟、可靠数据交换的应用场景。在设计和开发过程中，尽管中文文档提供了便利，但用户仍需查阅最新的英文数据手册（SNLS643），因为英文版的信息始终是最权威的，尤其是在技术规格和最新更新方面。TI强调，在正式设计前务必参考官方英文文档，以确保获取最准确的设计指导。

16-Bit

Word Count

ECC

Data ID

Data 0

Data 1

Data 2

Data 3

Data WC-4

Data WC-3

Data WC-2

Data WC-1

16-bit

Checksum

32-bit

PACKET

HEADER

(PH)

16-bit

PACKET

FOOTER

(PF)

PACKET DATA:

Length = Word Count (WC) * Data Word

Width (8-bits). There are NO restrictions

on the values of the data words

16-Bit

Short Packet

Data Field

VCX + ECC

Data ID

32-bit SHORT PACKET (SH)

Data Type (DT) = 0x00 ± 0x0F

DS90UB953A-Q1

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ZHCSJI8 –MARCH 2019

Feature Description (接接下下页页)

图图 5. CSI-2 Short Packet Structure

7.3.1.5 CSI-2 Long Packet

A long packet consists of three elements: a 32-bit packet header (PH), an application-specific data payload with

a variable number of 8-bit data words, and a 16-bit packet footer (PF). The packet header is further composed of

three elements: an 8-bit data identifier, a 16-bit word count field, and an 8-bit ECC. The packet footer only has

one element—a 16-bit checksum. 图 6 shows the structure of a long packet.

图图 6. CSI-2 Long Packet Structure

表表 1. CSI-2 Long Packet Structure Description

PACKET

PART

FIELD NAME SIZE (BIT) DESCRIPTION

Header

VC / Data ID 8 Contains the virtual channel identifier and the data-type information.

Word Count 16 Number of data words in the packet data. A word is 8 bits.

ECC 8

ECC for data ID and WC field. Allows 1-bit error recovery and 2-bit

error detection.

Data Data WC × 8 Application-specific payload (WC words of 8 bits).

Footer Checksum 16 16-bit cyclic redundancy check (CRC) for packet data.

7.3.1.6 CSI-2 Errors and Detection

7.3.1.6.1 CSI-2 ECC Detection and Correction

CSI-2 packet header contains 6-bit Error Correction Code (ECC). ECC in the 32-bit long packet header can be

corrected when there is a 1-bit error and detected when there is a 2-bit error. This feature is added to monitor the

CSI-2 input for ECC 1-bit error correction. When ECC error is detected, ECC error detection register will be set

and an alarm indicator bit can be sent to the deserializer to indicate the ECC error has been detected. A register

control can be used to either enable or disable the alarm. See the Specifications section for more information.

DS90UB953A-Q1

ZHCSJI8 –MARCH 2019

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7.3.1.6.2 CSI-2 Check Sum Detection

A CSI-2 long packet header contains a 16-bit check sum before the end of transmission. The DS90UB953A-Q1

calculates the check sum of the incoming CSI-2 data. If a check sum error is detected, the check sum error

status can be saved in the CSI_ERR_STATUS register (0x5D), then forwarded to the deserializer through the

bidirectional control channel.

7.3.1.6.3 D-PHY Error Detection

DS90UB953A-Q1 detect and reports SoT and SoT Sync errors.

7.3.1.6.4 CSI-2 Receiver Status

For the receive ports, several status functions can be tracked and monitored through register access. The status

indications are available for error conditions as well as indications of change in line length measurements. These

are available through the CSI_ERR_CNT (0x5C), CSI_ERR_STATUS (0x5D), CSI_ERR_DLANE01 (0x5E),

CSI_ERR_DLANE23 (0x5F), and CSI_ERR_CLK_LANE (0x60) registers.

7.3.2 FPD-Link III Forward Channel Transmitter

The DS90UB953A-Q1 features a high-speed signal transmitter capable of driving signals at rates of up to 4.16

Gbps.

7.3.2.1 Frame Format

The DS90UB953A-Q1 formats the data into 40-bit long frames. Each frame is encoded to ensure DC balance

and to ensure sufficient data line transitions. Each frame contains video payload data, I

C forward channel data,

CRC information, framing information, and information regarding the state of the CSI-2 interface.

7.3.3 FPD-Link III Back Channel Receiver

The FPD-Link III back channel receives an encoded back channel signal over the FPD-Link III interface. The

back channel frame is a 30-bit frame that contains I

C commands and GPIO data. The back channel frame

receives an encoded clock and data from the deserializer, thus the data bit rate is one-half the frequency of the

highest frequency received.

The back channel frequency is programmable for operation with compatible deserializers. The default setting is

determined by the MODE strap pin. For operation with the DS90UB954-Q1 or DS90UB960-Q1, the back channel

should be programmed for 50-Mbps operation in DS90UB953A-Q1 synchronous mode and programmed for 10-

Mbps operation for non-synchronous modes.

7.3.4 Serializer Status and Monitoring

The DS90UB953A-Q1 features enhanced FPD-Link III diagnostics, system monitoring, and Built-In Self Test

capabilities. The device monitors forward channel and back channel data for errors and reports them in the

status registers. The device also supports voltage and temperature measurement for system level diagnostics.

The Built-In Self Test feature allows testing of the forward channel and back channel data transmissions without

external data connections.

7.3.4.1 Forward Channel Diagnostics

The DS90UB953A-Q1 monitors the status of the forward channel link. The forward channel high-speed PLL lock

status is reported in the HS_PLL_LOCK bit (Register 0x52[2]). When paired with the DS90UB954-Q1, the FPD-

Link III deserializer LOCK status is also reported in the RX_LOCK_DETECT bit (Register 0x52[6]).

7.3.4.2 Back Channel Diagnostics

The DS90UB953A-Q1 monitors the status of the back channel link. The back channel CRC errors are reported in

the CRC_ERR bit (Register 0x52[1]). The number of CRC errors are stored in the CRC error counters and

reported in the CRC_ERR_CNT1 (Register 0x55) and CRC_ERR_CNT2 (Register 0x56) registers. The CRC

error counters are reset by setting the CRC_ERR_CLR (Register 0x49[3]) to 1.

Deserializer

BC_GPIOx

Serializer

GPIOx

Serializer

GPIOx

FPD-Link III

GPIOy

External

Frame Sync

DS90UB953A-Q1

ZHCSJI8 –MARCH 2019

www.ti.com.cn

7.3.4.3.1 Programming Example

This section gives an example on how to configure the DS90UB953A-Q1 and DS90UB954-Q1 to monitor the

voltage on the DS90UB953A-Q1 GPIO1 and set an alarm, which can then assert the INT pin on the

DS90UB954-Q1.

# DS90UB953A-Q1 Settings

WriteI2C(0x17,0x3E) # Enable Sensor, Select GPIO1 to sense

WriteI2C(0x18,0x80) # Enable Sensor Gain Setting (Use Default)

WriteI2C(0x1A,0x62) # Set Sensor Upper and Lower Limits (Use Default)

WriteI2C(0x1D,0x3F) # Enable Sensor Alarms

WriteI2C(0x1E,0x7F) # Enable Sending Alarms over BCC

# Register 0x57 readout (bits 2 and 3), indicates if the voltage on the GPIO1 is below or above the

thresholds set in the register 0x1A.

# DS90UB954-Q1 Settings

WriteI2C(0x23,0x81) # Enable Interrupts, Enable Interrupts for the camera attached to RX0

WriteI2C(0x4C,0x01) # Enable Writes to RX0 registers

WriteI2C(0xD8,0x08) # Interrupt on change in Sensor Status

# Register 0x51 and 0x52 readouts indicate Sensor data. Register 0x24[7] bit readout indicates the

Alarm bit. The alarm bit can be routed to GPIO3/INT through GPIO_PIN_CTL and GPIO_OUT_SRC registers.

7.3.4.4 Built-In Self Test

An optional at-speed Built-In Self Test (BIST) feature supports high-speed serial link and back channel testing

without external data connections. This is useful in the prototype stage, equipment production, in-system test,

and system diagnostics.

BIST mode is enabled by the BIST configuration register 0xB3[0] on the deserializer, and should only run in the

synchronous mode. When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer

through the back channel. The serializer outputs a continuous stream of a pseudo-random sequence and drives

the link at speed. The deserializer detects the test pattern and monitors the pattern for errors. The serializer also

tracks errors indicated by the CRC fields in each back channel frame. While the lock indications are required to

identify the beginning of proper data reception, the best indication of any link failures or data corruption is the

content of the error counter in the BIST_ERR_COUNT register 0x57 for each RX port on the deserializer side.

BIST mode is useful in the prototype stage, equipment production, in-system test, and system diagnostics.

7.3.5 FrameSync Operation

When paired with compatible deserializers, any of the DS90UB953A-Q1 GPIO pins can be use for frame

synchronization. This feature is useful when multiple sensors are connected to a deserializer hub. A frame

synchronization signal (FrameSync) can be sent through the back channel using any of the back channel GPIOs.

The FrameSync signal arrives at the serializers with limited skew.

7.3.5.1 External FrameSync

In External FrameSync mode, an external signal is input to the deserializer through one of the GPIO pins on the

device. The external FrameSync signal may be propagated to one or more of the attached FPD-Link III

serializers through a GPIO signal in the back channel. The expected skew timing for external FrameSync mode

is on the order of one back channel frame period or 600 ns when operating at 50 Mbps.

图图 7. External FrameSync

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