TI DS90UB953A-Q1：面向汽车应用的4.16Gbps FPD-Link III serializer for 2.3MP cameras

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DS90UB953A-Q1是一款专为汽车应用设计的高性能图像信号处理器(ISP)，它满足了AEC-Q100（1级）的严格标准，适用于工作温度范围在-40°C至+125°C的严苛环境。这款设备的核心功能是作为FPD-Link III的4.16Gbps串行接口，适用于2.3MP/60fps的高清摄像头、雷达探测器以及其他带CSI-2接口的传感器。 DS90UB953A-Q1的主要特性包括： 1. 高数据速率传输：它支持4.16Gbps的数据传输速率，能够无缝连接高速传感器，如1080p全高清和4MP的30fps图像传感器，确保图像数据的实时处理和传输。 2. 兼容性与标准支持：遵循D-PHYv1.2和CSI-2v1.3协议，提供了多达4条独立的数据通道，每通道最高832Mbps，同时支持虚拟通道技术，增强了系统的灵活性。 3. 精确时钟和同步：针对多摄像头应用，该器件具备精密的时钟管理和同步能力，确保各个摄像头间的精确同步，提高图像一致性。 4. 高级数据保护和诊断：内置CRC数据保护、传感器数据完整性检查、I2C写保护等功能，提供设备健康监控和故障检测，确保数据的安全性和系统的可靠性。 5. 电源选项：支持PoC（通过同轴电缆供电），也兼容屏蔽双绞线（STP）连接，方便在不同应用场景下部署。 6. I2C和HS-GPIO接口：提供了I2C接口，便于与其他控制器进行通信，以及高速GPIO接口，可以实现更多外部控制功能。 7. 文档资源：尽管中文版本的信息提供方便，但用户应参考最新的英文数据表SNLS643以获取最准确的技术细节，因为TI官网上的英文资料始终是最新的。 DS90UB953A-Q1是一款为汽车电子和工业应用打造的高性能图像信号处理器，它的特点在于高数据传输速率、精准时钟管理、强大的数据保护和广泛的接口支持，是现代图像采集系统中的关键组件。在实际设计过程中，务必确保使用官方的英文数据表进行详细研究。

16-Bit

Word Count

ECC

Data ID

Data 0

Data 1

Data 2

Data 3

Data WC-4

Data WC-3

Data WC-2

Data WC-1

16-bit

Checksum

32-bit

PACKET

HEADER

(PH)

16-bit

PACKET

FOOTER

(PF)

PACKET DATA:

Length = Word Count (WC) * Data Word

Width (8-bits). There are NO restrictions

on the values of the data words

16-Bit

Short Packet

Data Field

VCX + ECC

Data ID

32-bit SHORT PACKET (SH)

Data Type (DT) = 0x00 ± 0x0F

DS90UB953A-Q1

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ZHCSJI8 –MARCH 2019

Feature Description (接接下下页页)

图图 5. CSI-2 Short Packet Structure

7.3.1.5 CSI-2 Long Packet

A long packet consists of three elements: a 32-bit packet header (PH), an application-specific data payload with

a variable number of 8-bit data words, and a 16-bit packet footer (PF). The packet header is further composed of

three elements: an 8-bit data identifier, a 16-bit word count field, and an 8-bit ECC. The packet footer only has

one element—a 16-bit checksum. 图 6 shows the structure of a long packet.

图图 6. CSI-2 Long Packet Structure

表表 1. CSI-2 Long Packet Structure Description

PACKET

PART

FIELD NAME SIZE (BIT) DESCRIPTION

Header

VC / Data ID 8 Contains the virtual channel identifier and the data-type information.

Word Count 16 Number of data words in the packet data. A word is 8 bits.

ECC 8

ECC for data ID and WC field. Allows 1-bit error recovery and 2-bit

error detection.

Data Data WC × 8 Application-specific payload (WC words of 8 bits).

Footer Checksum 16 16-bit cyclic redundancy check (CRC) for packet data.

7.3.1.6 CSI-2 Errors and Detection

7.3.1.6.1 CSI-2 ECC Detection and Correction

CSI-2 packet header contains 6-bit Error Correction Code (ECC). ECC in the 32-bit long packet header can be

corrected when there is a 1-bit error and detected when there is a 2-bit error. This feature is added to monitor the

CSI-2 input for ECC 1-bit error correction. When ECC error is detected, ECC error detection register will be set

and an alarm indicator bit can be sent to the deserializer to indicate the ECC error has been detected. A register

control can be used to either enable or disable the alarm. See the Specifications section for more information.

DS90UB953A-Q1

ZHCSJI8 –MARCH 2019

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7.3.1.6.2 CSI-2 Check Sum Detection

A CSI-2 long packet header contains a 16-bit check sum before the end of transmission. The DS90UB953A-Q1

calculates the check sum of the incoming CSI-2 data. If a check sum error is detected, the check sum error

status can be saved in the CSI_ERR_STATUS register (0x5D), then forwarded to the deserializer through the

bidirectional control channel.

7.3.1.6.3 D-PHY Error Detection

DS90UB953A-Q1 detect and reports SoT and SoT Sync errors.

7.3.1.6.4 CSI-2 Receiver Status

For the receive ports, several status functions can be tracked and monitored through register access. The status

indications are available for error conditions as well as indications of change in line length measurements. These

are available through the CSI_ERR_CNT (0x5C), CSI_ERR_STATUS (0x5D), CSI_ERR_DLANE01 (0x5E),

CSI_ERR_DLANE23 (0x5F), and CSI_ERR_CLK_LANE (0x60) registers.

7.3.2 FPD-Link III Forward Channel Transmitter

The DS90UB953A-Q1 features a high-speed signal transmitter capable of driving signals at rates of up to 4.16

Gbps.

7.3.2.1 Frame Format

The DS90UB953A-Q1 formats the data into 40-bit long frames. Each frame is encoded to ensure DC balance

and to ensure sufficient data line transitions. Each frame contains video payload data, I

C forward channel data,

CRC information, framing information, and information regarding the state of the CSI-2 interface.

7.3.3 FPD-Link III Back Channel Receiver

The FPD-Link III back channel receives an encoded back channel signal over the FPD-Link III interface. The

back channel frame is a 30-bit frame that contains I

C commands and GPIO data. The back channel frame

receives an encoded clock and data from the deserializer, thus the data bit rate is one-half the frequency of the

highest frequency received.

The back channel frequency is programmable for operation with compatible deserializers. The default setting is

determined by the MODE strap pin. For operation with the DS90UB954-Q1 or DS90UB960-Q1, the back channel

should be programmed for 50-Mbps operation in DS90UB953A-Q1 synchronous mode and programmed for 10-

Mbps operation for non-synchronous modes.

7.3.4 Serializer Status and Monitoring

The DS90UB953A-Q1 features enhanced FPD-Link III diagnostics, system monitoring, and Built-In Self Test

capabilities. The device monitors forward channel and back channel data for errors and reports them in the

status registers. The device also supports voltage and temperature measurement for system level diagnostics.

The Built-In Self Test feature allows testing of the forward channel and back channel data transmissions without

external data connections.

7.3.4.1 Forward Channel Diagnostics

The DS90UB953A-Q1 monitors the status of the forward channel link. The forward channel high-speed PLL lock

status is reported in the HS_PLL_LOCK bit (Register 0x52[2]). When paired with the DS90UB954-Q1, the FPD-

Link III deserializer LOCK status is also reported in the RX_LOCK_DETECT bit (Register 0x52[6]).

7.3.4.2 Back Channel Diagnostics

The DS90UB953A-Q1 monitors the status of the back channel link. The back channel CRC errors are reported in

the CRC_ERR bit (Register 0x52[1]). The number of CRC errors are stored in the CRC error counters and

reported in the CRC_ERR_CNT1 (Register 0x55) and CRC_ERR_CNT2 (Register 0x56) registers. The CRC

error counters are reset by setting the CRC_ERR_CLR (Register 0x49[3]) to 1.

Deserializer

BC_GPIOx

Serializer

GPIOx

Serializer

GPIOx

FPD-Link III

GPIOy

External

Frame Sync

DS90UB953A-Q1

ZHCSJI8 –MARCH 2019

www.ti.com.cn

7.3.4.3.1 Programming Example

This section gives an example on how to configure the DS90UB953A-Q1 and DS90UB954-Q1 to monitor the

voltage on the DS90UB953A-Q1 GPIO1 and set an alarm, which can then assert the INT pin on the

DS90UB954-Q1.

# DS90UB953A-Q1 Settings

WriteI2C(0x17,0x3E) # Enable Sensor, Select GPIO1 to sense

WriteI2C(0x18,0x80) # Enable Sensor Gain Setting (Use Default)

WriteI2C(0x1A,0x62) # Set Sensor Upper and Lower Limits (Use Default)

WriteI2C(0x1D,0x3F) # Enable Sensor Alarms

WriteI2C(0x1E,0x7F) # Enable Sending Alarms over BCC

# Register 0x57 readout (bits 2 and 3), indicates if the voltage on the GPIO1 is below or above the

thresholds set in the register 0x1A.

# DS90UB954-Q1 Settings

WriteI2C(0x23,0x81) # Enable Interrupts, Enable Interrupts for the camera attached to RX0

WriteI2C(0x4C,0x01) # Enable Writes to RX0 registers

WriteI2C(0xD8,0x08) # Interrupt on change in Sensor Status

# Register 0x51 and 0x52 readouts indicate Sensor data. Register 0x24[7] bit readout indicates the

Alarm bit. The alarm bit can be routed to GPIO3/INT through GPIO_PIN_CTL and GPIO_OUT_SRC registers.

7.3.4.4 Built-In Self Test

An optional at-speed Built-In Self Test (BIST) feature supports high-speed serial link and back channel testing

without external data connections. This is useful in the prototype stage, equipment production, in-system test,

and system diagnostics.

BIST mode is enabled by the BIST configuration register 0xB3[0] on the deserializer, and should only run in the

synchronous mode. When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer

through the back channel. The serializer outputs a continuous stream of a pseudo-random sequence and drives

the link at speed. The deserializer detects the test pattern and monitors the pattern for errors. The serializer also

tracks errors indicated by the CRC fields in each back channel frame. While the lock indications are required to

identify the beginning of proper data reception, the best indication of any link failures or data corruption is the

content of the error counter in the BIST_ERR_COUNT register 0x57 for each RX port on the deserializer side.

BIST mode is useful in the prototype stage, equipment production, in-system test, and system diagnostics.

7.3.5 FrameSync Operation

When paired with compatible deserializers, any of the DS90UB953A-Q1 GPIO pins can be use for frame

synchronization. This feature is useful when multiple sensors are connected to a deserializer hub. A frame

synchronization signal (FrameSync) can be sent through the back channel using any of the back channel GPIOs.

The FrameSync signal arrives at the serializers with limited skew.

7.3.5.1 External FrameSync

In External FrameSync mode, an external signal is input to the deserializer through one of the GPIO pins on the

device. The external FrameSync signal may be propagated to one or more of the attached FPD-Link III

serializers through a GPIO signal in the back channel. The expected skew timing for external FrameSync mode

is on the order of one back channel frame period or 600 ns when operating at 50 Mbps.

图图 7. External FrameSync

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