STM32F071x8/STM32F071xB微控制器数据手册

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Functional overview STM32F071x8 STM32F071xB

16/122 DS10009 Rev 7

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example on

failure of an indirectly used external crystal, resonator or oscillator).

Figure 2. Clock tree

Several prescalers allow the application to configure the frequency of the AHB and the APB

domains. The maximum frequency of the AHB and the APB domains is 48 MHz.

MSv31419V4

OSC_IN

OSC_OUT

OSC32_IN

OSC32_OUT

IWDG

PLLMUL

MCO

Main clock

output

PLLCLK

HSI

HSE

PLLCLK

ADC

asynchronous

clock input

LSE

LSI

HSI

HSE

RTC

PLLSRC

MCO

RTCCLK

RTCSEL

SYSCLK

TIM1,2,3,6,7,

14,15,16,17

FLITFCLK

Flash memory

programming

interface

HSI14

LSE

I2C1

USART1

LSE

HSI

SYSCLK

PCLK

SYSCLK

HSI

PCLK

I2S1/SPI1

I2S2/SPI2

CEC

APB

peripherals

LSI

LSE

PREDIV

HSI48

PLLNODIV

MCOPRE

TIM14

LSE

HSE

LSE

SYNC

CSS

Trim

Legend

white

clock tree control element

clock line

control line

black

clock tree element

/32

4-32 MHz

HSE OSC

/1,/2,/4,

/8,/16

/1,/2

14 MHz RC

HSI14

/1,/2,…

…/512

8 MHz

HSI RC

/1,/2,..

../16

32.768 kHz

LSE OSC

40 kHz

LSI RC

PLL

x2,x3,..

...x16

48 MHz

HSI RC

x1, x2

/1,/2,/4,..

../128

USARTxSW

PPRE

PPREHPRE

CECSW

/244

I2C1SW

SYSCLK

CRS

HSI

HSI48

HSI

SYNCSRC

USART2

HCLK

AHB, core, memory, DMA,

Cortex FCLK free-run clock

Cortex

system timer

DS10009 Rev 7 17/122

STM32F071x8 STM32F071xB Functional overview

Additionally, also the internal RC 48 MHz oscillator can be selected for system clock or PLL

input source. This oscillator can be automatically fine-trimmed by the means of the CRS

peripheral using the external synchronization.

3.7 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions.

The I/O configuration can be locked if needed following a specific sequence in order to

avoid spurious writing to the I/Os registers.

3.8 Direct memory access controller (DMA)

The 7-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory

and memory-to-peripheral transfers.

The DMA supports circular buffer management, removing the need for user code

intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

DMA can be used with the main peripherals: SPIx, I2Sx, I2Cx, USARTx, all TIMx timers

(except TIM14), DAC and ADC.

3.9 Interrupts and events

3.9.1 Nested vectored interrupt controller (NVIC)

The STM32F0xx family embeds a nested vectored interrupt controller able to handle up to

32 maskable interrupt channels (not including the 16 interrupt lines of Cortex

-M0) and 4

priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

Functional overview STM32F071x8 STM32F071xB

18/122 DS10009 Rev 7

3.9.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 32 edge detector lines used to generate

interrupt/event requests and wake-up the system. Each line can be independently

configured to select the trigger event (rising edge, falling edge, both) and can be masked

independently. A pending register maintains the status of the interrupt requests. The EXTI

can detect an external line with a pulse width shorter than the internal clock period. Up to 87

GPIOs can be connected to the 16 external interrupt lines.

3.10 Analog-to-digital converter (ADC)

The 12-bit analog-to-digital converter has up to 16 external and 3 internal (temperature

sensor, voltage reference, VBAT voltage measurement) channels and performs conversions

in single-shot or scan modes. In scan mode, automatic conversion is performed on a

selected group of analog inputs.

The ADC can be served by the DMA controller.

An analog watchdog feature allows very precise monitoring of the converted voltage of one,

some or all selected channels. An interrupt is generated when the converted voltage is

outside the programmed thresholds.

3.10.1 Temperature sensor

The temperature sensor (TS) generates a voltage V

SENSE

that varies linearly with

temperature.

The temperature sensor is internally connected to the ADC_IN16 input channel which is

used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall

accuracy of the temperature measurement. As the offset of the temperature sensor varies

from chip to chip due to process variation, the uncalibrated internal temperature sensor is

suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is

individually factory-calibrated by ST. The temperature sensor factory calibration data are

stored by ST in the system memory area, accessible in read-only mode.

3.10.2 Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

) provides a stable (bandgap) voltage output for the

ADC and comparators. V

REFINT

is internally connected to the ADC_IN17 input channel. The

Table 3. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS ADC raw data acquired at a

temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7B8 - 0x1FFF F7B9

TS_CAL2

TS ADC raw data acquired at a

temperature of 110 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7C2 - 0x1FFF F7C3

DS10009 Rev 7 19/122

STM32F071x8 STM32F071xB Functional overview

precise voltage of V

REFINT

is individually measured for each part by ST during production

test and stored in the system memory area. It is accessible in read-only mode.

3.10.3 V

BAT

battery voltage monitoring

This embedded hardware feature allows the application to measure the V

BAT

battery voltage

using the internal ADC channel ADC_IN18. As the V

BAT

voltage may be higher than V

DDA

and thus outside the ADC input range, the V

BAT

pin is internally connected to a bridge

divider by 2. As a consequence, the converted digital value is half the V

BAT

voltage.

3.11 Digital-to-analog converter (DAC)

The two 12-bit buffered DAC channels can be used to convert digital signals into analog

voltage signal outputs. The chosen design structure is composed of integrated resistor

strings and an amplifier in non-inverting configuration.

This digital Interface supports the following features:

• 8-bit or 12-bit monotonic output

• Left or right data alignment in 12-bit mode

• Synchronized update capability

• Noise-wave generation

• Triangular-wave generation

• Dual DAC channel independent or simultaneous conversions

• DMA capability for each channel

• External triggers for conversion

Six DAC trigger inputs are used in the device. The DAC is triggered through the timer trigger

outputs and the DAC interface is generating its own DMA requests.

3.12 Comparators (COMP)

The device embeds two fast rail-to-rail low-power comparators with programmable

reference voltage (internal or external), hysteresis and speed (low speed for low power) and

with selectable output polarity.

The reference voltage can be one of the following:

• External I/O

• DAC output pins

• Internal reference voltage or submultiple (1/4, 1/2, 3/4).Refer to Table 28: Embedded

internal reference voltage for the value and precision of the internal reference voltage.

Table 4. Internal voltage reference calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at a

temperature of 30 °C (± 5 °C),

DDA

= 3.3 V (± 10 mV)

0x1FFF F7BA - 0x1FFF F7BB

Functional overview STM32F071x8 STM32F071xB

20/122 DS10009 Rev 7

Both comparators can wake up from STOP mode, generate interrupts and breaks for the

timers and can be also combined into a window comparator.

3.13 Touch sensing controller (TSC)

The STM32F071x8/xB devices provide a simple solution for adding capacitive sensing

functionality to any application. These devices offer up to 24 capacitive sensing channels

distributed over 8 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which

is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation

introduced by the finger (or any conductive object) is measured using a proven

implementation based on a surface charge transfer acquisition principle. It consists in

charging the sensor capacitance and then transferring a part of the accumulated charges

into a sampling capacitor until the voltage across this capacitor has reached a specific

threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the

hardware touch sensing controller and only requires few external components to operate.

For operation, one capacitive sensing GPIO in each group is connected to an external

capacitor and cannot be used as effective touch sensing channel.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware

library, which is free to use and allows touch sensing functionality to be implemented reliably

in the end application.

Table 5. Capacitive sensing GPIOs available on STM32F071x8/xB devices

Group

Capacitive sensing

signal name

name

Group

Capacitive sensing

signal name

name

TSC_G1_IO1 PA0

TSC_G5_IO1 PB3

TSC_G1_IO2 PA1 TSC_G5_IO2 PB4

TSC_G1_IO3 PA2 TSC_G5_IO3 PB6

TSC_G1_IO4 PA3 TSC_G5_IO4 PB7

TSC_G2_IO1 PA4

TSC_G6_IO1 PB11

TSC_G2_IO2 PA5 TSC_G6_IO2 PB12

TSC_G2_IO3 PA6 TSC_G6_IO3 PB13

TSC_G2_IO4 PA7 TSC_G6_IO4 PB14

TSC_G3_IO1 PC5

TSC_G7_IO1 PE2

TSC_G3_IO2 PB0 TSC_G7_IO2 PE3

TSC_G3_IO3 PB1 TSC_G7_IO3 PE4

TSC_G3_IO4 PB2 TSC_G7_IO4 PE5

TSC_G4_IO1 PA9

TSC_G8_IO1 PD12

TSC_G4_IO2 PA10 TSC_G8_IO2 PD13

TSC_G4_IO3 PA11 TSC_G8_IO3 PD14

TSC_G4_IO4 PA12 TSC_G8_IO4 PD15

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