STM32F103高性能ARM Cortex-M3 MCU技术规格

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"STM32F103是意法半导体（STMicroelectronics）生产的一款高性能、高密度32位微控制器，属于STM32系列。该芯片基于ARM公司的Cortex-M3内核，具备多种功能特性，适用于各种嵌入式应用。" STM32F103芯片的主要特点和功能包括： 1. **核心处理器**：采用ARM Cortex-M3 32位处理器，工作频率高达72MHz，提供每MHz 1.25 DMIPS/MHz的性能，在0等待状态内存访问下，运算速度非常快。此外，它还支持单周期乘法和硬件除法操作，提高了计算效率。 2. **内存配置**：STM32F103提供了256KB到512KB的闪存（Flash）存储空间，以及最多64KB的SRAM。另外，它的灵活静态内存控制器（FSMC）支持4个芯片选择，可兼容CompactFlash、SRAM、PSRAM、NOR和NAND等多种内存类型。此外，该芯片还具有LCD并行接口，支持8080和6800模式。 3. **时钟、复位和电源管理**：芯片工作电压范围为2.0V到3.6V，支持POR（上电复位）、PDR（掉电复位）和可编程电压检测器（PVD）。它内置4到16MHz的晶体振荡器、8MHz的工厂校准RC振荡器以及一个40kHz的校准RC振荡器，用于RTC（实时计时器）。 4. **低功耗设计**：STM32F103支持睡眠、停止和待机三种低功耗模式，VBAT供电可用于RTC（实时时钟）和备份寄存器，确保在电池供电下也能保持基本功能。 5. **模拟转换器**：集成3个12位的A/D转换器，转换速度最快可达1微秒，可处理多达21个输入通道，适合对模拟信号进行快速采样和转换。 6. **通信接口**：STM32F103包含丰富的通信接口，如USB、CAN和多达13种不同的通信接口，这使得它能够方便地与其他设备进行数据交换和系统集成。 7. **定时器和ADC**：芯片内含11个定时器，3个ADC，这些定时器和ADC可以用于精确控制任务调度和信号处理，广泛应用于电机控制、传感器接口等场景。 8. **GPIO**：拥有丰富的通用输入输出（GPIO）端口，可以根据需要配置为不同功能，增强了系统的灵活性。 STM32F103是一款功能强大、适应性强的32位微控制器，适合于需要高速处理、多种外设接口和低功耗特性的应用，例如工业自动化、物联网设备、消费电子和嵌入式控制系统等。

Description STM32F103xC, STM32F103xD, STM32F103xE

16/144 DocID14611 Rev 12

2.3.6 LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

2.3.7 Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex

-M3) and 16 priority levels.

• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core

• Closely coupled NVIC core interface

• Allows early processing of interrupts

• Processing of late arriving higher priority interrupts

• Support for tail-chaining

• Processor state automatically saved

• Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.8 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

2.3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

DocID14611 Rev 12 17/144

STM32F103xC, STM32F103xD, STM32F103xE Description

136

2.3.10 Boot modes

At startup, boot pins are used to select one of three boot options:

• Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

memory bank 2 by setting a bit in the option bytes.

• Boot from system memory

• Boot from embedded SRAM

The boot loader is located in system memory. It is used to reprogram the Flash memory by

using USART1.

2.3.11 Power supply schemes

• V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

• V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset

blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC

or DAC is used). V

DDA

and V

SSA

must be connected to V

and V

, respectively.

• V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 12: Power supply scheme.

2.3.12 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

higher than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.13 Voltage regulator

The regulator has three operation modes: main (MR), low-power (LPR) and power down.

• MR is used in the nominal regulation mode (Run)

• LPR is used in the Stop modes.

• Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

Description STM32F103xC, STM32F103xD, STM32F103xE

18/144 DocID14611 Rev 12

2.3.14 Low-power modes

The STM32F103xC, STM32F103xD and STM32F103xE performance line supports three

low-power modes to achieve the best compromise between low-power consumption, short

startup time and available wakeup sources:

• Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

• Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low-power mode.

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB

wakeup.

• Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers. The two DMA controllers support circular buffer management,

removing the need for user code intervention when the controller reaches the end of the

buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

The DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose, basic

and advanced-control timers TIMx, DAC, I

S, SDIO and ADC.

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit

registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

Description STM32F103xC, STM32F103xD, STM32F103xE

20/144 DocID14611 Rev 12

Advanced-control timers (TIM1 and TIM8)

The two advanced-control timers (TIM1 and TIM8) can each be seen as a three-phase

PWM multiplexed on 6 channels. They have complementary PWM outputs with

programmable inserted dead-times. They can also be seen as a complete general-purpose

timer. The 4 independent channels can be used for:

• Input capture

• Output compare

• PWM generation (edge or center-aligned modes)

• One-pulse mode output

If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If

configured as the 16-bit PWM generator, it has full modulation capability (0-100%).

In debug mode, the advanced-control timer counter can be frozen and the PWM outputs

disabled to turn off any power switch driven by these outputs.

Many features are shared with those of the general-purpose TIM timers which have the

same architecture. The advanced-control timer can therefore work together with the TIM

timers via the Timer Link feature for synchronization or event chaining.

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)

embedded in the STM32F103xC, STM32F103xD and STM32F103xE performance line

devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler

and feature 4 independent channels each for input capture/output compare, PWM or one-

pulse mode output. This gives up to 16 input captures / output compares / PWMs on the

largest packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug

mode. Any of the general-purpose timers can be used to generate PWM outputs. They all

have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from

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