TMS416169: 高速16位EDO DRAM技术规格

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"TI1-TMS416169.pdf" TI1-TMS416169.pdf 文件描述了一种高性能的动态随机存取内存（DRAM）芯片，包括TMS416169和TMS418169型号。这两种内存芯片都采用了德州仪器（Texas Instruments, TI）的Enhanced Performance Implanted CMOS (EPIC)工艺，旨在提供高速度、高可靠性和低功耗的存储解决方案。 1. **内存规格与组织结构** - TMS416169和TMS418169是16位扩展数据输出（Extended Data Out, EDO）DRAM，总共有16777216位的存储容量，即1MB。 - 内存被组织为1048576个16位字，这意味着每个设备有1024K（1048576/1024）个64KB的存储块。 2. **电源与性能** - 这些内存芯片只需要单个5V电源供应，简化了系统设计。 - 性能参数包括访问时间（Access Time）、读写周期时间和数据输出时间等，具体分为三个速度等级：'41x169/P-60、'41x169/P-70和'41x169/P-80，分别对应60ns、70ns和80ns的最大访问时间。 3. **EDO操作模式** - EDO技术允许数据在地址稳定后继续在时钟周期的上升沿之前输出，从而提高数据传输速率。 4. **刷新机制** - 支持xCAS-Before-RAS(xCBR)刷新模式，这种模式下，列地址可以在行地址之前进行预充电，提高了数据读取效率。 - 提供两种刷新模式：TMS418169支持1024周期的刷新，在16毫秒内完成；而TMS416169支持4096周期的刷新，在64毫秒内完成。 5. **输出特性** - 内置3态未锁存的输出，允许在不同操作模式下灵活控制数据输出。 6. **封装与物理特性** - 采用高可靠性塑料42引脚封装（DZ后缀），尺寸为400 mil宽的表面贴装SOJ（Small Outline J-lead）包。 - 具有0°C至70°C的操作自由空气温度范围，适应广泛的环境条件。 7. **工艺技术** - EPIC工艺是TI的专有技术，它优化了晶体管性能，提高了芯片的速度和耐用性，同时降低了功耗。这些DRAM芯片适用于需要高性能、低功耗和高可靠性的系统，例如个人计算机、服务器和各种嵌入式系统。它们的特性使其成为当时先进内存技术的代表，能够满足高速数据处理和频繁存取的需求。

TMS416169, TMS418169

1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS

SMKS886C – MAY1995– REVISED MARCH 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

data in (DQ0–DQ15) (continued)

delayed-write or read-modify-write cycle, xCAS

is already low and the data is strobed in by W with setup and

hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE

must be high to bring the

output buffers to the high-impedance state prior to impressing data on the I/O lines.

data out (DQ0–DQ15)

Data out is the same polarity as data-in. The output is in the high-impedance (floating) state until xCAS

and OE

are brought low. In a read cycle, the output becomes valid after the access time interval t

CAC

(which begins with

the negative transition of xCAS

) as long as t

RAC

and t

are satisfied.

output enable (OE

)

controls the impedance of the output buffers. While xCAS and RAS are low and W is high, OE can be brought

low or high and the DQs switch from valid data to high impedance. There are two methods for placing the DQs

into the high-impedance state and keeping them in that state during xCAS

high time using OE. The first method

is to switch OE

high before xCAS goes high and keep OE high for t

CHO

past the CAS transition. This disables

the DQs and they remain in the high-impedance state, regardless of OE

, until xCAS falls again. The second

method is to have OE

low as xCAS transitions high. Then OE can pulse high for a minimum of t

OEP

anytime

during CAS

high time disabling the DQs regardless of further transitions on OE until CAS falls again.

RAS

-only refresh

TMS416169

A refresh operation must be performed at least once every 64 ms to retain data. This is achieved by strobing

each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits in each row that is selected.

A RAS

-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the

output buffers remain in the high-impedance state. Externally generated addresses must be used for a

RAS

-only refresh.

TMS418169

A refresh operation must be performed at least once every 16 ms to retain data. This is achieved by strobing

each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in each row that is selected. A

RAS

-only operation can be used by holding both xCAS at the high (inactive) level, conserving power as the

output buffers remain in the high-impedance state. Externally generated addresses must be used for a

RAS

-only refresh.

hidden refresh

Hidden refresh can be performed while maintaining valid data at the output pins. This is accomplished by holding

xCAS

at V

after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only

refresh cycle. The external address is ignored and the refresh address is generated internally.

xCAS

-before-RAS (xCBR) refresh

xCBR refresh is achieved by bringing at least one xCAS

low earlier than RAS (see parameter t

CSR

) and holding

it low after RAS

falls (see parameter t

CHR

). For successive xCBR refresh cycles, xCAS can remain low while

cycling RAS

. The external address is ignored and the refresh address is generated internally.

power-up

To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles

is required after power-up to the full V

level. These eight initialization cycles must include at least one refresh

(RAS

-only or xCBR) cycle.

TMS416169, TMS418169

1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS

SMKS886C – MAY1995– REVISED MARCH 1996

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

– 1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any pin (see Note 1) – 1 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short-circuit output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to V

recommended operating conditions

’41x169

UNIT

MIN NOM MAX

UNIT

Supply voltage 4.5 5 5.5 V

Supply voltage 0 V

High-level input voltage 2.4 6.5 V

Low-level input voltage (see Note 2) –1 0.8 V

Operating free-air temperature 0 70

°C

NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.

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