Xilinx 7系列FPGA SelectIO 中英文用户手册解析

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"ug471_7Series_SelectIO_中英文对照" 这篇文档是Xilinx公司针对7系列FPGA的SelectIO资源提供的用户指南，中英文对照版，旨在帮助读者更高效地理解和使用SelectIO特性。文档版本为UG471(v1.10)，发布日期为2018年5月8日，经过多次修订，提供了关于SelectIO的详细信息和指导。 7系列FPGA SelectIO是Xilinx FPGA架构中的一个重要组成部分，它允许灵活配置输入/输出(I/O)接口，以适应各种不同的应用需求。这些资源包括可编程的I/O标准、电压电平转换、驱动器强度和接收器均衡等功能，使得FPGA能够与各种外部设备进行高效通信。用户指南详细介绍了如何选择和配置SelectIO资源，包括但不限于以下几个方面： 1. **I/O标准**：SelectIO支持多种电气标准，如LVCMOS、LVTTL、LVDS、HSTL等，用户可以根据实际连接的外部设备选择合适的I/O标准。 2. **电压电平转换**：7系列FPGA的SelectIO支持不同电压等级的输入和输出，可以在同一芯片上处理多种电压等级的信号，适应不同电源环境。 3. **驱动器强度**：可以根据负载条件调整I/O驱动器的电流大小，确保信号质量并减少功耗。 4. **接收器均衡**：提供眼图开大和信号恢复功能，以改善高速信号的传输质量，特别是在长线缆或高噪声环境中。 5. **I/O bank和I/O引脚分配**：介绍如何有效地分配和组织SelectIO资源，以优化布线和减少信号延迟。 6. **时序约束**：指导如何设置时序约束，确保I/O操作满足系统时钟和同步要求。 7. **错误检测和保护机制**：讨论了可能的故障情况以及如何通过内置的错误检测和保护功能来增强系统的可靠性。此外，文档还强调了使用Xilinx产品时的一些法律责任和免责声明。Xilinx明确指出，提供的材料按“原样”提供，不保证无误，且不承担任何直接或间接损失的责任。特别是对于关键应用和汽车应用，Xilinx强调其产品并未设计为故障安全，用户在使用于这些领域时应自行承担风险，并确保符合相关安全标准。在使用这份用户指南时，读者应注意Xilinx提供的保修政策和IP内核许可条款，这些信息可能在指定的网址中查阅。同时，对于汽车应用，如果涉及安全关键系统，用户必须进行充分的安全评估和设计，以满足ISO26262等汽车安全标准。 "7Series_FPGA_SelectIO"用户指南是开发者和工程师在利用7系列FPGA进行系统设计时的重要参考资料，它提供了全面的SelectIO资源配置和使用的详细指导。通过深入理解和应用这些知识，可以有效提高FPGA设计的灵活性、性能和可靠性。

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Chapter 1: SelectIO Resources

Figure 1-2:

Figure 1-3:

Figure 1-4:

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7系列FPGASelectIO资源用户指南UG471(v1.10)2

018年5月8日

X-Ref目标图1-2

常规HPIOB图

X-Ref目标图1-3

单端（仅）HRIOB图

X-Ref目标图1-4

常规HRIOB图

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Chapter 1: SelectIO Resources

X-Ref Target - Figure 1-2

Figure 1-2: Regular HP IOB Diagram

X-Ref Target - Figure 1-3

Figure 1-3: Single-Ended (Only) HR IOB Diagram

X-Ref Target - Figure 1-4

Figure 1-4: Regular HR IOB Diagram

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Chapter 1: SelectIO Resources

CCO

REF

CCAUX

CCAUX_IO

7系列FPGASelectIO资源用户指南UG471(v1.10)2

018年5月8日

SelectIO引脚的电源电压

VCCO电源是7系列IO电路的主电源。表1-55中的VCCO(V)列提供了每个受支持的IO标准的

VCCO要求，并说明了输入和输出以及可选的内部差分终端电路的VCCO要求。给定IObank

的所有VCCO引脚必须连接到板上相同的外部电压电源，因此给定IObank内的所有IO必须共

享相同的VCCO电平。VCCO电压必须符合已分配给IO组的IO标准的要求。不正确的VCCO

电压可能会导致设备功能丧失或损坏。7系列FPGA数据手册中描述了7系列电源要求，包括

上电和断电排序。

在HPIObank中，如果IO标准电压要求<1.8V，但施加的VCCO>2.5V，则器件自动进入过压

保护模式。使用正确的VCCO电平重新配置器件可恢复正常操作。

具有差分输入缓冲器的单端IO标准需要输入参考电压(VREF)。当IObank中需要VREF时，该b

ank的两个多功能VREF引脚必须用作VREF电源输入。通过启用INTERNAL_VREF约束，7系列

FPGA可以选择使用内部生成的参考电压。有关此约束的更多信息，请参阅7系列FPGASelec

tIO属性约束，第46页。

全局辅助(VCCAUX)电源轨主要用于为7系列FPGA内的各种模块功能的互连逻辑供电。在IO

bank中，VCCAUX还用于为某些IO标准的输入缓冲电路供电。其中包括1.8V或以下的所有

单端IO标准，以及一些2.5V标准（仅限HRIO组）。此外，VCCAUX轨为用于差分和VREFIO

标准的组的差分输入缓冲电路供电。

7系列FPGA数据手册中描述了7系列电源要求，包括上电和断电排序。

辅助IO(VCCAUX_IO)电源轨仅存在于HPIObank中，并为IO电路供电。Kintex-7和Virtex-7F

PGA数据表包含标题为内存接口的最大物理接口(PHY)速率的表格，该表格引用了VCCAUX_

IO。此表说明VCCAUX_IO引脚如何以1.8V（默认）或可选的2.0V供电，以实现某些类型的

存储器接口的更高频率性能。尽管此表是为存储器接口设计的，但它也可以为基于目标比

特率的其他高速单端接口的VCCAUX_IO供电提供指导。该表不适用于LVDS，它使用与受V

CCAUX_IO电平影响更大的单端驱动器不同类型的驱动器电路。因此，对于LVDS接口，VC

CAUX_IO轨的供电电压电平无关紧要。默认值1.8V可提供更低的功耗，并在IOs中提供非常

接近相同的性能。当单端驱动器支持的最快比特率需要略微提高性能时，可以使用2.0V选

项。

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UG471 (v1.10) May 8, 2018

Chapter 1: SelectIO Resources

Supply Voltages for the SelectIO Pins

CCO

The V

CCO

supply is the primary power supply of the 7 series I/O circuitry. The V

CCO (V)

columns in Table 1-55 provide the V

CCO

requirements for each of the supported I/O

standards, and illustrate the V

CCO

requirements for both inputs and outputs as well as the

optional internal differential termination circuit. All V

CCO

pins for a given I/O bank must

be connected to the same external voltage supply on the board, and as a result all of the

I/O within a given I/O bank must share the same V

CCO

level. The V

CCO

voltage must

match the requirements for the I/O standards that have been assigned to the I/O bank. An

incorrect V

CCO

voltage can result in loss of functionality or damage to the device. The

7 series power supply requirements, including power-on and power-off sequencing, are

described in the 7 series FPGA data sheets.

In HP I/O banks, if the I/O standard voltage requirement is <

1.8V, but a V

CCO

> 2.5V is

applied, the device automatically enters an overvoltage protection mode. Reconfiguring

the device with the correct V

CCO

level restores normal operation.

REF

Single-ended I/O standards with a differential input buffer require an input reference

voltage (V

REF

). When V

REF

is required within an I/O bank, the two multi-function V

REF

pins for the bank must be used as V

REF

supply inputs. 7 series FPGAs can optionally use an

internally generated reference voltage by enabling the INTERNAL_VREF constraint. For

more information on this constraint, see 7 Series FPGA SelectIO Attributes/Constraints,

page 46.

CCAUX

The global auxiliary (V

CCAUX

) supply rail is prima r il y us ed for providing power to the

various block feature’s interconnect logic insi de the 7 series FPGAs. In the I/O banks,

CCAUX

is also used to power input buffer circuits for some of the I/O standards. These

include all of the single-ended I/O standards at or below 1.8V, and also some of the 2.5V

standards (HR I/O bank s only ). Additionally, the V

CCAUX

rail provides power to the

bank’s differential input buffer circuits used for the differential and V

REF

I/O standards.

The 7 series power supply requirements, including power-on and power-off sequencing,

are described in the 7 series FPGA data sheets.

CCAUX_IO

The auxiliary I/O (V

CCAUX_IO

) supply rail is only present in HP I/O banks and provid es

power to the I/O circuitry. The Kintex-7 and Virtex-7 FPGAs data sheets contain a table

titled Maximum Physical Interface ( PH Y ) Rate for Memory Interfaces that references

CCAUX_IO

. This table indicates how the V

CCAUX_IO

pins can be powered at either 1.8V

(default), or optionally at 2.0V to achieve higher frequency performance for certain types

of memory interfaces. Although this table is designed for memory interfaces, it can also

provide guidance on powering V

CCAUX_IO

for other high-speed single-ended interfaces

based on the target bit rates. The table does not apply to LVDS, which uses a different type

of driver circuit than the single-ended drivers that are more affected by the V

CCAUX_IO

level. Thus, for LVDS interfaces, it does not matter which voltage level the V

CCAUX_IO

rail

is powered at. The default value of 1.8V affords a lower-power consumption and provides

very close to the same performance in the I/Os. The 2.0V option is available when the

slightly-increased performance is required for the very fastest bit rates supported for the

single-ended drivers.

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UG471 (v1.10) May 8, 2018

Introduction

7系列FPGASelectIO资源用户指南

7系列FPGADCI—仅在HPIObank中可用

IO网络和原语有一个称为VCCAUX_IO的设计约束，如果要将任何bank的VCCAUX_IO引脚

设置为2.0V，则应在设计中指定该约束。有关此约束的信息，请参见第46页的7系列FPGAS

electIO属性约束。

VCCAUX_IO引脚在Kintex-7和Virtex-7器件封装内部以三个或四个HPIObank为一组连接在

一起。UG475的封装文件章节：7系列FPGA封装和引脚分配规范包含指向ASCII封装文件的

链接，器件图一章中的数字指示哪些器件封装组合包含带有VCCAUX_IO引脚的HPIObank。

ASCII封装文件指示封装内将哪个bank的VCCAUX_IO管脚组合在一起。VCCAUX_IO封装管

脚名称的语法为VCCAUX_IO_G#，其中#是内部组号。封装文件包含一个名为“VCCAUXGr

oup”的列，该列显示每个IO引脚与IObank关联的VCCAUX组。同一个VCCAUX_IO组中的所

有IO管脚必须在其兼容的网络或原语上具有VCCAUX_IO约束。组合在一起的所有VCCAUX_

IO引脚应连接到板上的同一电压轨。Kintex-7器件的FBG封装包含VCCAUX_IO引脚，但内

部没有连接。这些封装中的所有HPIObank都由主VCCAUX轨供电。

配置期间和配置后IOs的状态

7系列FPGA具有专用于IObank0中的配置功能的管脚。bank14和15还包含称为多功能或多

用途管脚的IO管脚，它们也可用于配置，但在配置后转换为普通IO管脚已经完成。此外，

在SSI器件中，bank11、12、17、18、20和21中的管脚在配置期间具有类似于多功能管脚

的限制。但是，这些bank中的管脚没有任何配置功能。

在bank14和/或bank15为HRbank且配置为VCCO要求<1.8V的器件中，如果输入连接到0或

浮动且配置电压>2.5V。有关详细信息，请参阅UG470：7系列FPGA配置用户指南。

7系列FPGADCI—仅在HPIObank中可用

随着FPGA变得越来越大，系统时钟速度越来越快，PC板的设计和制造变得更加困难。随

着边缘速率越来越快，保持信号完整性成为一个关键问题。PC板走线必须正确端接以避

免反射或振铃。

为了终止迹线，传统上添加电阻器以使输出和/或输入匹配接收器或驱动器的阻抗与迹线的

阻抗。然而，由于器件IOs增加，在器件引脚附近添加电阻器会增加电路板面积和元件数量

，并且在某些情况下可能在物理上是不可能的。为了解决这些问题并实现更好的信号完整

性，Xilinx开发了数控阻抗(DCI)技术。

根据IO标准，DCI可以控制驱动器的输出阻抗，也可以在驱动器和/或接收器上添加一个并

行终端，以精确匹配传输线的特性阻抗。DCI主动调整IO内部的这些阻抗，以校准放置在VR

N和VRP引脚上的外部精密参考电阻器。这补偿了IO的变化

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UG471 (v1.10) May 8, 2018

7 Series FPGA DCI—Only available in the HP I/O banks

There is a design constraint for I/O nets and primitives called VCCAUX_IO, which should

be specified in the design if the V

CCAUX_IO

pins for any banks are to be set at 2.0V. See

7 Series FPGA SelectIO Attributes/Constraints, page 46 for information on this constraint.

The V

CCAUX_IO

pins are connected together internally inside Kintex-7 and Virtex-7 device

packages in groups of three or four HP I/O banks. The package files chapter of

UG475

: 7 Series FPGA Packaging and Pinout Specification contains links to the ASCII package

files, and the figures in the device diagrams chapter indicate which device/package

combinations contain HP I/O banks with V

CCAUX_IO

pins. The ASCII package files

indicate which bank’s V

CCAUX_IO

pins are grouped together inside the package. The

CCAUX_IO

package pin names have the syntax VCCAUX_IO_G#, where the # is the

internal group number. The package files cont ain a column called “VCCAUX Group” that

shows for every I/O pin which V

CCAUX

group that I/O bank is associated with. All I/O

pins that are in the same V

CCAUX_IO

group must have VCCAUX_IO constraints on their

nets or primitives that are compatible. All V

CCAUX_IO

pins that are grouped together

should be tied to the same voltag e rai l on the board. FBG packages for Kintex-7 devices

contain V

CCAUX_IO

pins but are no connects internally. All HP I/O banks in those packages

are powered from the main V

CCAUX

rail instead.

State of I/Os During and After Configuration

7 series FPGAs have pins dedicated to configuration functions contained in I/O bank 0.

Banks 14 and 15 also contain I/O pins known as multi-function or multi-purpose pins that

can also be used for configuration, but then conve rt to normal I/O pins after configuration

is complete. Additionally in SSI devices, pins in banks 11, 12, 17, 18, 20, and 21 have

restrictions during configuration similar to multi-function pins. However, pins in these

banks do not have any configuration functions.

In devices where bank 14 and/or bank 15 are HR banks and configured with a V

CCO

requirement <

1.8V, inputs might have a 0-1-0 transition to the interconnect logic during

configuration if the input is tied to 0 or floating and the configuration voltage is >

2.5V. For

further details, refer to UG470

: 7 Series FPGAs Configuration User Guide.

7 Series FPGA DCI—Only available in the HP I/O banks

Introduction

As FPGAs get bigger and system clock speeds get faster, PC board design and

manufacturing becomes more difficult. With ever faster edge rates, maintaining signal

integrity becomes a critical issue. PC board traces must be properly terminated to avoid

reflections or ringing.

To terminate a trace, resistors are traditionally added to make the outpu t and/or input

match the impedance of the re ceiver or driver to the impedance of the trace. However, due

to increased device I/Os, adding resistors clos e to the device pins increases the board area

and component count, and can in some cases be physically impossible. To address these

issues and to achieve better signal integrity, Xilinx developed the digitally controlled

impedance (DCI) technology.

Depending on the I/O standard, DCI can e ither control the output impedance of a driver,

or add a parallel termination present at the driver and/or receiver, with the goal of

accurately matching the characteristic impedance of the transmission line. DCI actively

adjusts these impedances inside the I/O to calibrate to external precision reference

resistors placed on the VRN and VRP pins. This compensates for changes in I/O

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Chapter 1: SelectIO Resources

Xilinx DCI

7系列FPGASelectIO资源用户指南UG471(v1.10)2

018年5月8日

由于工艺变化的阻抗。它还连续调整阻抗以补偿温度和电源电压波动的变化。

对于具有受控阻抗驱动器的IO标准，DCI控制驱动器阻抗以匹配两个参考电阻器，或者对于

某些标准，匹配这些参考电阻器的一半值。

对于具有受控并行终端的IO标准，DCI为发送器和接收器提供并行终端。这消除了板上端

接电阻的需要，减少了电路板布线困难和组件数量，并通过消除短截线反射提高了信号完

整性。当终端电阻距离传输线末端太远时，会发生短截线反射。使用DCI，端接电阻器尽

可能靠近输出驱动器或输入缓冲器，从而消除短截线反射。DCI仅在7系列FPGAHPIObank

中可用。DCI在HRIObank中不可用。

DCI在每个IObank中使用两个多用途参考引脚来控制驱动器的阻抗或该bank的所有IOs的并

联终端值。N参考引脚(VRN)必须通过参考电阻上拉至VCCO，并且P参考引脚(VRP)必须通过

另一个参考电阻下拉至地。每个参考电阻的值应等于PC板走线的特性阻抗或该值的两倍。

要在设计中实现DCI：

在HPIObank中分配DCIIO标准之一（请参见表1-2和表1-3）。

将VRN多功能引脚连接到一个精密电阻，该电阻连接到同一组的VCCO轨。

将VRP多功能引脚连接到接地的精密电阻。

以下部分讨论如何确定不同IO标准的VRN和VRP的精密电阻值。每个bank仅使用一组VRN和

VRP电阻，因此每个bank内的所有DCI标准必须能够共享相同的外部电阻值。如果同一IOba

nk列中的多个IObank使用DCI，并且所有这些IObank使用相同的VRNVRP电阻值，则内部VR

N和VRP节点可以级联，以便所有IObank仅使用一对引脚在整个IO列中需要连接精密电阻。

此选项称为DCI级联，详见DCI级联，第22页。本节还介绍了如何确定IObank是否共享相同

的IObank列。如果组中未使用DCIIO标准，则这些引脚可用作常规IO引脚。UG475：7系列

FPGA封装和管脚规范给出了详细的管脚描述。

DCI通过选择性地打开或关闭IOs中的晶体管来调整IO的阻抗。调整阻抗以匹配外部参考电

阻。调整在设备启动序列期间开始。默认情况下，在阻抗调整过程的第一部分完成之前，D

ONE引脚不会变为高电平。

DCI校准可以通过例化DCIRESET原语来复位。在设备运行时将RST输入切换到DCIRESET原语

，重置DCI状态机并重新启动校准过程。在DCIRESET模块的LOCKED输出被断言之前，所有

使用DCI的IOs都将不可用。此功能在温度和/或电源电压从器件上电到标称工作条件显着变

化的应用中非常有用。

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UG471 (v1.10) May 8, 2018

Chapter 1: SelectIO Resources

impedance due to process variation. It also continuously adjusts the impedances to

compensate for variations of temperature and supply voltage fluctuations.

For the I/O standards with controlled impedance drivers, DCI controls the driver

impedance to either match the two reference resi stors, or for some standards, to match half

the value of these reference resistors.

For the I/O standards with controlled parallel termination, DCI provides the parallel

termination for both transmitters and receivers. This eliminates the need for termination

resistors on the board, reduces board routing difficulties and component count, and

improves signal integrity by elim inat ing stub

reflection. Stub reflection occurs when

termination resistors are located too far from the end of the transmission line. With DCI,

the termination resistors are as close as possible to the output driver or the input buffer,

thus, eliminating stub reflections. DCI is only avail abl e in 7 series FPGAs HP I/O banks.

DCI is not available in HR I/O banks.

Xilinx DCI

DCI uses two multi-purpose reference pins in each I/O bank to control the impedance of

the driver or the parallel-termination value for all of the I/Os of that bank. The N reference

pin (VRN) must be pulled up to V

CCO

by a reference resistor, and the P reference pin (VRP)

must be pulled down to ground by another reference resistor. The value of each reference

resistor should be either equal to the characteristic impedance of the PC board traces or

twice that value.

To implement DCI in a design:

1. Assign one of the DCI I/O standards in an HP I/O bank (see Table 1-2 and Table 1-3).

2. Connect the VRN multi-function pin to a precision resistor tied to the V

CCO

rail for the

same bank.

3. Connect the VRP multi-function pin to a precision resistor tied to ground.

The following sections discuss how to determine the precision resistor values for VRN and

VRP for the different I/O standards. Only one set of VRN and VRP resistors is used for

each bank, so all DCI standards within each bank must be able to share the same external

resistance values. If several I/O banks in the same I/O bank column are using DCI, and all

of those I/O banks use the same VRN/VRP re

sistor values, the internal VRN and VRP

nodes can be cascaded so that only one pair of pins for all of the I/O banks in the entire I/

O column is required to be connected to precision resistors. This option is called DCI

cascading and is detailed in DCI Cascading, page 22. This section also describes how to

determine if I/O banks share the same I/O bank column. If DCI I/O standards are not

used in the bank, these pins are available as regular I/O pins. UG475

: 7 Series FPGAs

Packaging and Pinout Specifications gives detailed pin descriptions.

DCI adjusts the impedance of the I/O by selectively turning transistors in the I/Os on or

off. The impedance is adjusted to match the external r eference re sistors . Th e a djustment

starts during the device startup sequence. By default, the DONE pin does not go High until

the first part of the impedance adjustment process is completed.

The DCI calibration can be reset by instantiating the DCIRESET primitive. Toggling the

RST input to the DCIRESET primitive while the device is operating, resets the DCI state

machine and restarts the calibration process. All I/Os using DCI will be unavailable until

the LOCKED output from the DCIRESET block is asserted. This funct ional ity is useful in

applications where the temperature and/or supply voltage changes significantly from

device power-up to the nominal operating condition.

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