TLV320AIC10：Σ-Δ型高精度D/A和A/D转换器详解

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TLV320AIC10是一款高性能的Σ-Δ型重采样高分辨率数字化音频处理器，它集成了16位同步串行AD（Analog-to-Digital Converter）和DAC（Digital-to-Analog Converter）。这款芯片在音频信号处理领域具有显著的优势，特别适合于需要高精度转换的场合，如音频信号的采集、处理和播放。该芯片的主要特点包括： 1. **高分辨率转换**: 16位的数据精度确保了输出的音频质量接近无损，能够提供细腻的声音表现，满足音频发烧友和专业应用的需求。 2. **多种数据传输模式**: 支持同步串行输入输出，这使得它能够灵活地与其他数字信号处理器（DSP）进行接口，便于系统级集成和优化。 3. **寄存器编程控制**：通过编程不同的寄存器设置，用户可以调整工作模式、采样率、数据格式等参数，实现对转换过程的精细控制。 4. **与DSP通信**：内置的通信接口使得TLV320AIC10能够无缝地与数字信号处理器协作，共同完成音频处理任务，提升系统效率。 5. **兼容性与更新性**：请注意，使用前务必查询最新的SLWS093C文档，因为德州仪器（TI）可能会根据产品发展需要进行更改或停止服务，因此建议获取最新的技术规格和销售条款以确保信息的准确性和完整性。 6. **保修政策**：TI对其半导体产品按照销售时适用的标准保修政策提供保障，但并非对所有参数进行全面测试，除非政府有强制规定。用户需自行负责应用中的问题。 7. **责任归属**：在使用过程中，客户应自行承担应用中使用TI部件的所有责任，这意味着需要了解和遵守芯片的使用限制和条件。 TLV320AIC10是一款专为音频系统设计的高性能AD/DA转换器，适合那些追求音质和系统集成度的音频设备制造商。但在实际应用中，确保对最新资料的掌握，并了解产品的特性和限制是至关重要的。

1–4

1.3 Terminal Assignments

14 15

DD2

M/S

ALTIN

DCSI

AURXFP

AURXM

AURXCP

DTXOP

DTXOM

DTXIP

DTXIM

OUTP

OUTM

PWRDWN

17 18 19 20

FILT

47 46 45 44 4348 42

INM

INP

FLAG

DIN

SCLK

MCLK

FSD

40 39 3841

22 23 24

VMID

RESET

DOUT

PFB PACKAGE

(TOP VIEW)

DD1

NOTE: All NC pins should be left unconnected.

1.4 Ordering Information

PACKAGE

48-TQFP PFB

0°C to 70°C TLV320AIC10C

–40°C to 85°C TLV320AIC10I

1.5 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

ALTIN 26 I Serial input in the

event monitor

mode

AURXCP 3 I Receiver-path/GP amplifier noninverting input. It needs to be connected to AV

if not used.

AURXM 2 I Receiver-path amplifier A1 inverting input, or inverting input to auxiliary analog input. It needs to be connected to

if not used. Can also be used for general-purpose amplification.

AURXFP 1 I Receiver-path amplifier A1 feedback, or noninverting input to auxiliary analog input. It needs to be connected to

if not used. Can also be used for general-purpose amplification.

DD1

DD2

I Analog ADC power supply

33, 40,

42, 46

I Analog ground

DCSI 25 I Direct configuration serial input for directly programming of internal control registers

DIN 17 I Data input. DIN receives the DAC input data and register data from the external digital signal processor (DSP),

and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at high

impedance when FS is not activated.

DOUT 16 O Data output. DOUT transmits the ADC output bits and registers data, and is synchronized to SCLK and FS. Data is

sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not activated.

1–5

1.5 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

DTXIM 7 I Transmitter-path amplifier A3 analog inverting input. Can also be used for general-purpose amplification.

DTXIP 6 I Transmitter-path amplifier A4 analog noninverting input. Can also be used for general-purpose amplification.

DTXOM 5 O Transmitter path amplifier A4 feedback for negative output. Can also be used for general-purpose

amplification.

DTXOP 4 O Transmitter path amplifier A3 feedback for positive output. Can also be used for negative output.

DD1

15 I Digital power supply

DD2

30 I Digital power supply

14, 29 I Digital ground

FC 24 I Hardware request for secondary communication

FILT 38 O Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 2.5 V. The optimal

capacitor value is 0.1 µF (ceramic). This voltage node should be loaded only with a high-impedance dc load.

FLAG 23 O Controlled by bit D4 of control register 3. If D4=0 (default), the FLAG pin outputs the communication flag that

goes low/high to indicate primary-communication/secondary-communication interval, respectively. If D4=1,

the FLAG pin outputs the value of D3.

FS 22 I/O Frame sync. When FS goes low, DIN begins receiving data bits and DOUT begins transmitting data bits. In

master mode, FS is internally generated and is low during data transmission to DIN and from DOUT. In slave

mode, FS is externally generated.

FSD 21 O Frame-sync delayed output. The FSD output synchronizes a slave device to the frame sync of the master

device. FSD is applied to the slave FS input and has the same duration as the master FS signal. Requires a

pullup resistor if not used.

INM 48 I Inverting input to analog modulator. INM requires an external R-C antialias filter with low output impedance if

the internal antialias filter is bypassed.

INP 47 I Noninverting input to analog modulator. INP requires an external R-C antialias filter with low output impedance

if the internal antialias filter is bypassed.

M0 10 I Combine with M1 to select serial interface mode (frame-sync mode)

M1 11 I Combine with M0 to select serial interface mode (frame-sync mode)

MCLK 20 I Master clock. MCLK derives the internal clocks of the sigma-delta analog interface circuit.

M/S 27 I Master/slave select input. When M/S is high, the device is the master, and when is low, it is a slave.

NC 18, 28, 31,

32, 35, 36,

37, 39, 41,

No connection

OUTM 9 O DAC’s inverting output. OUTM is functionally identical with and complementary to OUTP.

OUTP 8 O DAC’s noninverting output. OUTP can also be used alone for single-ended operation.

PWRDWN 12 I Power down. When PWRDWN is pulled low, the device goes into a power-down mode, the serial interface is

disabled, and most of the high-speed clocks are disabled. However, all register values are sustained and the

device resumes full-power operation without reinitialization when PWRDWN is pulled high again. PWRDWN

resets the counters only and preserves the programmed register contents. See paragraph 2.2.2 for more

information.

RESET 13 I Reset. The reset function is provided to initialize all the internal registers to their default values. The serial port

can be configured to the default state accordingly. See Appendix A,

, and Subsection 2.2.1,

Reset

and Power-Down Functions

for detailed descriptions.

SCLK 19 I/O Shift clock. SCLK signal clocks serial data into DIN and out of DOUT during the frame-sync interval. When

configured as an output (M/S

high), SCLK is generated internally by multiplying the frame-sync signal

frequency by 256 (cascade devices < 5) or 512 (cascade devices > 4). When configured as an input (M/S low),

SCLK is generated externally and must be synchronous with the master clock and frame sync.

VMID 43 O Reference voltage output at AVDD/2

1–6

1.6 Definitions and Terminology

Data transfer interval The time during which data is transferred from DOUT to DIN. The interval is 16 shift clocks and the

data transfer is initiated by the falling edge of the FS signal.

Signal data This refers to the input signal and all of the converted representations through the ADC channel, and

the signal through the DAC channel to the analog output. This is in contrast with the purely-digital

software control data.

Primary

communication

Primary communication refers to the digital data-transfer interval. Since the device is synchronous,

the signal data words from the ADC channel and to the DAC channel occur simultaneously.

Secondary

communication

Secondary communication refers to the digital control and configuration data-transfer interval into

DIN, and the register read-data cycle from DOUT. The data transfer occurs when requested by hard-

ware or software.

SPI Serial peripheral interface standard set by Motorola

Frame/pulse sync Frame/pulse sync refers only to the falling edge of the signal FS that initiates the data-transfer inter-

val. The primary FS starts the primary communication, and the secondary FS starts the secondary

communication.

Frame/pulse sync and

sampling period

Frame/pulse sync and sampling period is the time between falling edges of successive primary FS

signals and it is always equal to 256xSCLK if the number of cascading devices is less than 5, or 512

xSCLK if the number of cascading devices is greater than 4.

The sampling frequency

ADC channel ADC channel refers to all signal-processing circuits between the analog input and the digital

conversion result at DOUT.

DAC channel DAC channel refers to all signal-processing circuits between the digital data word applied to DIN and

the differential output analog signal available at OUTP and OUTM.

Host A host is any processing system that interfaces to DIN, DOUT, SCLK, FS, and/or MCLK.

Dxx Bit position in the primary data word (xx is the bit number).

DSxx Bit position in the secondary data word (xx is the bit number).

d The alpha character

represents valid programmed or default data in the control-register format

(see Section 3.2,

Secondary Serial Communication

) when discussing other data bit portions of the

PGA Programmable gain amplifier

FIR Finite-duration impulse response

DCSI Direct configuration serial interface for host control

1.7 Register Functional Summary

There are five control registers which are used as follows:

other registers.

• Produce the output flag to indicate a decimator FIR filter overflow (read cycle only)

• Enable of general-purpose operational amplifiers A1, A3, and A4

• Enable/bypass ADC’s analog antialiasing filter

• Select normal or auxiliary analog input

• Control 16-bit or (15+1)-bit mode of DAC operation

• Enable/bypass the decimator FIR filter

• Enable/bypass the interpolator FIR filter

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