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K60 Sub-Family官方手册:Cortex-M4核心与模块详解
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更新于2024-07-21
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本资源是一份官方发布的《K60子家族参考手册》,主要针对飞思卡尔(Kalypso)的K60系列微控制器,如MK60DN256VLQ10、MK60DX256VLQ10、MK60DN512VLQ10等型号。该手册的版本为Rev.2,发布日期为2012年6月,处于预览阶段。
手册详细介绍了K60系列产品的各种特性和支持功能,旨在帮助开发者理解和利用这些硬件平台。以下部分是部分内容概要:
1. **关于文档**:
- 1.1 范围:手册的目的是为了提供K60子家族详细的技术文档,包括其核心功能、模块分类以及配置选项。
- 1.1.1 目标受众:读者主要是嵌入式系统设计师、工程师和开发人员,他们需要了解K60系列的硬件设计细节。
- 1.2 符号与约定:文档中采用了统一的编号系统、排版规则,并定义了一些特定的术语,以确保清晰和一致的交流。
2. **引言**:
- 2.1 简介:这部分概述了K60系列的总体架构,强调其基于ARM Cortex-M4内核的强大处理能力。
- 2.2 模块分类:
- ARMCortex-M4核心模块:重点介绍处理器核心的特性和性能。
- 系统模块:涵盖了电源管理、中断控制器、看门狗定时器等系统级组件。
- 内存和接口:讨论了片上存储器和与外部设备通信的接口。
- 时钟系统:详细说明了时钟配置和管理功能。
- 安全与完整性:涉及安全模块,如加密和身份验证功能。
- 模拟模块:可能包括模拟信号处理和测量单元。
- 计时器模块:为精确时间管理提供了多种选择。
- 通信接口:支持的串行、并行以及网络通信接口。
- 人机交互接口:涉及USB、触摸屏、按键等输入输出设备。
3. **芯片配置**:
- 3.1 引导读者理解如何配置K60系列芯片的参数,包括不同版本之间的差异和功能调整。
- 通过详细介绍芯片配置选项,帮助开发人员优化系统性能和实现定制化需求。
这份K60子家族参考手册为使用飞思卡尔K60系列微控制器的开发者提供了一个全面的指南,涵盖了核心硬件的各个方面,有助于在设计和开发过程中快速定位和利用相关功能。对于任何正在或计划使用此类芯片的工程师来说,这是一份不可或缺的参考资料。
Section number Title Page
19.3.8 Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................417
19.4 Functional description...................................................................................................................................................419
19.4.1 Access evaluation macro..............................................................................................................................419
19.4.2 Putting it all together and error terminations...............................................................................................420
19.4.3 Power management......................................................................................................................................421
19.5 Initialization information..............................................................................................................................................421
19.6 Application information................................................................................................................................................421
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................425
20.1.1 Features........................................................................................................................................................425
20.1.2 General operation.........................................................................................................................................426
20.2 Memory map/register definition...................................................................................................................................426
20.2.1 Master Privilege Register A (AIPSx_MPRA).............................................................................................428
20.2.2 Peripheral Access Control Register (AIPSx_PACRn).................................................................................431
20.2.3 Peripheral Access Control Register (AIPSx_PACRn).................................................................................436
20.3 Functional description...................................................................................................................................................441
20.3.1 Access support.............................................................................................................................................441
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................443
21.1.1 Overview......................................................................................................................................................443
21.1.2 Features........................................................................................................................................................444
21.1.3 Modes of operation......................................................................................................................................444
21.2 External signal description............................................................................................................................................445
21.3 Memory map/register definition...................................................................................................................................445
21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................446
21.4 Functional description...................................................................................................................................................447
21.4.1 DMA channels with periodic triggering capability......................................................................................447
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Preliminary
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General Business Information
Section number Title Page
21.4.2 DMA channels with no triggering capability...............................................................................................449
21.4.3 "Always enabled" DMA sources.................................................................................................................449
21.5 Initialization/application information...........................................................................................................................450
21.5.1 Reset.............................................................................................................................................................451
21.5.2 Enabling and configuring sources................................................................................................................451
Chapter 22
Direct Memory Access Controller (eDMA)
22.1 Introduction...................................................................................................................................................................455
22.1.1 Block diagram..............................................................................................................................................455
22.1.2 Block parts...................................................................................................................................................456
22.1.3 Features........................................................................................................................................................457
22.2 Modes of operation.......................................................................................................................................................459
22.3 Memory map/register definition...................................................................................................................................459
22.3.1 Control Register (DMA_CR).......................................................................................................................470
22.3.2 Error Status Register (DMA_ES)................................................................................................................472
22.3.3 Enable Request Register (DMA_ ERQ ).....................................................................................................474
22.3.4 Enable Error Interrupt Register (DMA_ EEI ).............................................................................................476
22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................479
22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................480
22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................481
22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................482
22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................483
22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................484
22.3.11 Clear Error Register (DMA_CERR)............................................................................................................485
22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................486
22.3.13 Interrupt Request Register (DMA_ INT )....................................................................................................487
22.3.14 Error Register (DMA_ ERR )......................................................................................................................489
22.3.15 Hardware Request Status Register (DMA_ HRS )......................................................................................492
22.3.16 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................494
K60 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
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General Business Information
Section number Title Page
22.3.17 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................495
22.3.18 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................495
22.3.19 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................496
22.3.20 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................497
22.3.21 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................497
22.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................498
22.3.23 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................500
22.3.24 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................500
22.3.25 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................501
22.3.26 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................501
22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................502
22.3.28 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........503
22.3.29 TCD Control and Status (DMA_TCDn_CSR)............................................................................................504
22.3.30 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................506
22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................507
22.4 Functional description...................................................................................................................................................508
22.4.1 eDMA basic data flow.................................................................................................................................508
22.4.2 Error reporting and handling........................................................................................................................511
22.4.3 Channel preemption.....................................................................................................................................513
22.4.4 Performance.................................................................................................................................................513
22.5 Initialization/application information...........................................................................................................................518
22.5.1 eDMA initialization.....................................................................................................................................518
22.5.2 Programming errors.....................................................................................................................................520
K60 Sub-Family Reference Manual, Rev. 2 Jun 2012
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Preliminary
Freescale Semiconductor, Inc.
General Business Information
Section number Title Page
22.5.3 Arbitration mode considerations..................................................................................................................520
22.5.4 Performing DMA transfers (examples)........................................................................................................521
22.5.5 Monitoring transfer descriptor status...........................................................................................................525
22.5.6 Channel Linking...........................................................................................................................................526
22.5.7 Dynamic programming................................................................................................................................528
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................533
23.1.1 Features........................................................................................................................................................533
23.1.2 Modes of Operation.....................................................................................................................................534
23.1.3 Block Diagram.............................................................................................................................................535
23.2 EWM Signal Descriptions............................................................................................................................................536
23.3 Memory Map/Register Definition.................................................................................................................................536
23.3.1 Control Register (EWM_CTRL).................................................................................................................536
23.3.2 Service Register (EWM_SERV)..................................................................................................................537
23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................537
23.3.4 Compare High Register (EWM_CMPH).....................................................................................................538
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................539
23.4 Functional Description..................................................................................................................................................539
23.4.1 The EWM_out Signal..................................................................................................................................539
23.4.2 The EWM_in Signal....................................................................................................................................540
23.4.3 EWM Counter..............................................................................................................................................541
23.4.4 EWM Compare Registers............................................................................................................................541
23.4.5 EWM Refresh Mechanism...........................................................................................................................541
23.4.6 EWM Interrupt.............................................................................................................................................542
23.4.7 Counter clock prescaler................................................................................................................................542
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................543
K60 Sub-Family Reference Manual, Rev. 2 Jun 2012
Freescale Semiconductor, Inc.
Preliminary
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General Business Information
Section number Title Page
24.2 Features.........................................................................................................................................................................543
24.3 Functional overview......................................................................................................................................................545
24.3.1 Unlocking and updating the watchdog.........................................................................................................546
24.3.2 Watchdog configuration time (WCT)..........................................................................................................547
24.3.3 Refreshing the watchdog..............................................................................................................................548
24.3.4 Windowed mode of operation......................................................................................................................548
24.3.5 Watchdog disabled mode of operation.........................................................................................................548
24.3.6 Low-power modes of operation...................................................................................................................549
24.3.7 Debug modes of operation...........................................................................................................................549
24.4 Testing the watchdog....................................................................................................................................................550
24.4.1 Quick test.....................................................................................................................................................550
24.4.2 Byte test........................................................................................................................................................551
24.5 Backup reset generator..................................................................................................................................................552
24.6 Generated resets and interrupts.....................................................................................................................................552
24.7 Memory map and register definition.............................................................................................................................553
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................554
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................555
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................556
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................556
24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................557
24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................557
24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................558
24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................558
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................558
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................559
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................559
24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................560
24.8 Watchdog operation with 8-bit access..........................................................................................................................560
24.8.1 General guideline.........................................................................................................................................560
K60 Sub-Family Reference Manual, Rev. 2 Jun 2012
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Preliminary
Freescale Semiconductor, Inc.
General Business Information
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