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首页BCM89820:100Mbps汽车以太网单端口收发器规格详解
BCM89820:100Mbps汽车以太网单端口收发器规格详解
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更新于2024-07-18
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博通BCM89820规格书详细介绍了这款专为汽车行业设计的高性能100兆比特每秒(Mbps)以太网收发器。该芯片集成了一个单片CMOS集成电路,具备强大的物理层(PHY)功能,支持基于BroadR-Reach编码的以太网数据包在单对无屏蔽双绞线(如FlexRay)上进行传输。其目标是满足严苛的汽车工业标准,包括噪声消除和传输抖动控制,确保在各种现有的单对双绞线汽车电缆基础设施中提供稳定且可靠的通信。 BCM89820采用了Broadcom成熟的数字信号处理技术,其中包括数字自适应均衡器、模数转换器(ADC)、锁相环(PLL)、线路驱动器、编码器、解码器以及必要的支持电路。这款器件完全符合标准的Serial Gigabit Media Independent Interface (SGMII) 规范,这意味着它兼容业界标准的以太网媒体访问控制器,确保与各种设备的无缝连接。 其特性亮点包括: 1. 高带宽:100 Mbps的数据速率,适用于需要高速通信的汽车应用。 2. 集成设计:单一芯片解决方案,简化了系统设计和布局。 3. 物理层优化:针对汽车环境的噪声抑制和传输稳定性进行了专门优化。 4. FlexRay支持:能够处理像FlexRay这样的实时通信协议,适合关键的汽车网络系统。 5. 标准接口兼容:通过SGMII接口实现广泛的应用场景和设备集成。 BCM89820的设计旨在应对汽车行业中对可靠性和耐用性的极高要求,确保在复杂且多变的车辆电气环境中保持高效稳定的通信。这对于现代汽车电子架构,如自动驾驶、车载信息娱乐系统以及车联网等领域来说,是一个至关重要的组件。
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Forced BroadR-Reach ModeBCM89820 Preliminary Data Sheet
BROADCOM CONFIDENTIAL
Broadcom
®
September 14, 2016 • 89820-DS100-R Page 16
Forced BroadR-Reach Mode
To configure the PHY into forced one-pair 100 Mb/s BroadR-Reach mode, program the two PHYs in the link
segment to set LRE register 00h to:
• 0200h for 100 Mb/s one-pair BroadR-Reach slave
• 0208h for 100 Mb/s one-pair BroadR-Reach master
Each BroadR-Reach link segment requires one link partner to be slave and one BroadR-Reach link partner to
be master.
Energy Detect
The energy-detect feature provides an output signal (Energy Detect) indicating the presence or absence of
energy being received on the copper analog input pins of the chip. Additionally, the copper energy-detection
status can be monitored from register 1Ch, shadow 11111, bit 5. See “Operational Description” for details.
Power-Down Modes
Two low-power modes are supported in the BCM89820:
• Ultralow power-down mode (IDDQ)
• Standby power-down mode
Jumbo Packets
In copper mode, packets up to 10 KB in length can be supported with the following register writes:
• Register 18h, shadow 000, bit 14 = 1 (default = 0)
• Register 10h, bit 0 = 1 (default = 0)
![](https://csdnimg.cn/release/download_crawler_static/10557253/bg11.jpg)
Hardware Signal DescriptionsBCM89820 Preliminary Data Sheet
BROADCOM CONFIDENTIAL
Broadcom
®
September 14, 2016 • 89820-DS100-R Page 17
Section 2: Hardware Signal Descriptions
The following conventions are used in Table 2:
• I: Input
• O: Output
• I/O: Bidirectional
• OD: Open-drain output
• OT: Tristateable signal
•B: Bias
• PU: Internal pull-up
• PD: Internal pull-down
• SOR: Sample on reset
• CS: Continuously sampled
• ST: Schmitt trigger
The following conventions are used to express the I/O types in Table 2. The I/O pin type is useful in referencing
the DC pin characteristics contained in Section 7: “Electrical Characteristics”:
• A: Analog pin type
• D: Digital pin type
• DNC: Do not connect
• G: RGMII pin type
• GND: General ground
• PECL: Positive Emitter Coupled Logic
• S: SerDes pin type
• XT: Crystal inputs/outputs pin type
Note: Pin groups that are not found on a certain package are represented by an en dash (–).
Note: Refer to the BCM89820 Design Guide Application Note for additional information regarding the
configurations and bypassing of the power supply pins.
Table 2: Hardware Signal Descriptions
100-Pin
FBGA
Label
I/O
Type
Description
Media Connections
K3
K4
TRD[0]± A Transmit/Receive Pairs
In BroadR-Reach mode, differential data from copper media is transmitted
and received on the TRD± signal pair. There are 50 internal termination
on each pin, so no external termination is required.
3 TVCOI O Copper PLL Test Clock Output
![](https://csdnimg.cn/release/download_crawler_static/10557253/bg12.jpg)
Hardware Signal DescriptionsBCM89820 Preliminary Data Sheet
BROADCOM CONFIDENTIAL
Broadcom
®
September 14, 2016 • 89820-DS100-R Page 18
SerDes/SGMII
A2
A3
TXDP
TXDN
O
S
SGMII Data Output
Differential serial data output.
A1
B1
RXDP
RXDN
I
S
SGMII Data Input
Differential serial data input when BCM89820 is in SGMII mode. These
pins have a 100 differential termination resistor on-chip.
Clocks
D1 CLK125 O,G MAC Reference Clock
Continuous 125 MHz output generated off the PLL (phase locked to the
CLKP/CLKN input). This clock output remains active and stable during
both hardware and software reset. This clock is powered by OVDD power.
F1
G1
CLKP
CLKN
XT
XT
25 MHz Clock Reference Pins for Entire Device.
Can be configured to either differential input or XTAL (crystal oscillator)
type.
J3 TVCOI O Copper PLL Test Clock Output.
Reference Clock Selection
D9
C4
REFCLK_SEL[0]
REFCLK_SEL[1]
I
PD
I
PD
Clock Reference Selector
Allows user to select the type of input clock reference signal.
REFCLK_SEL[1]: REFCLK_SEL[0]: Clock Modes:
0 0 Selects differential reference clock
inputs (CLKP, CLKN).
0 1 Selects single-ended CMOS.
1 0 Selects XTAL input.
1 1 Not allowed.
F7 CLKSEL_125 I
PD
125 MHz Input Reference Clock Enable
Allows user to supply a 125 MHz clock signal on pins CLKP/CLKN (F1/
G1) instead of a 25 MHz clock.
0: 25 MHz input reference clock on pins CLKP/CLKN
1: 125 MHz input reference clock on pins CLKP/CLKN
MDIO
B3 MDC I
PD
,
ST
Management Data Clock
The MDC clock input must be provided to allow MII management
functions. When configured as BSC_SLAVE, this pin becomes the SCL
pin of the BSC interface.
B2 MDIO I/O
PU
,
D, ST
Management Data I/O
This serial input/output bit is used to read from and write to the MII
registers. The data value on the MDIO pin is valid and latched on the rising
edge of MDC. When configured as BSC_SLAVE, this pin becomes the
SDA pin of the BSC interface.
Table 2: Hardware Signal Descriptions (Cont.)
100-Pin
FBGA
Label
I/O
Type
Description
![](https://csdnimg.cn/release/download_crawler_static/10557253/bg13.jpg)
Hardware Signal DescriptionsBCM89820 Preliminary Data Sheet
BROADCOM CONFIDENTIAL
Broadcom
®
September 14, 2016 • 89820-DS100-R Page 19
Mode
B5
G9
H8
H9
H7
PHYA[0]
PHYA[1]
PHYA[2]
PHYA[3]
PHYA[4]
I
PD
,
SOR
PHY Address Selects
Active high. Sampled on reset. The PHY address selects the MII
management PHY address. The device goes into isolate mode when the
PHY address is strapped to 00000. To get out of isolate mode, write
register 00h, bit 10 = 0.
A8
B7
INTERF_SEL[0]
INTERF_SEL[1]
I
PD
Interface Mode Selector.
Allows configuration of device to support SGMII to copper mode.
INTERF_SEL[1] INTERF_SEL[0] Interface Modes
0 0 Reserved
0 1 Reserved
1 0 SGMII-copper
1 1 Reserved
C2 RESET
I
PU
,
CS,
ST
RESET
Active low, Schmitt Trigger Input. The BCM89820 requires a hardware
RESET
prior to normal operation. Configuration settings obtained via
hardware strap option pins are latched on the rising edge of RESET
.
C3 LED1 I
PU
, O LED1/ANEN
This is a dual function pin.
Output polarity is determined at reset. See “Dual-Input Configuration/LED
Output Function” for details. This pin can be programmed to alternate
modes. See “General-Purpose LED Programmability” for details.
Copper Auto-Negotiation Enable Select. Active high. Sampled on reset.
When this pin is high, copper auto-negotiation is enabled. When low,
copper auto-negotiation is disabled. After reset, auto-negotiation
configuration is under software control.
B4 LED2 I
PU
, O LED2/Full Duplex
This is a dual function pin.
Output polarity is determined at reset. See “Dual-Input Configuration/LED
Output Function” for details. This pin can be programmed to alternate
modes. See “General-Purpose LED Programmability” for details.
Full-duplex Select. Active high. Sampled on reset. When this pin is high,
full-duplex is enabled. When low, full-duplex is disabled. After reset, full-
duplex configuration is under software control.
E4 LED3 I
PU
, O LED3/LED4
Output polarity is determined at reset. See “Dual-Input Configuration/LED
Output Function” for details.
Programmed to alternate modes. See “General-Purpose LED
Programmability” for details.
If this pin is programmed to output interrupts, it becomes an open-drain
output.
C5 LED4 I
PU
,
O, OD
Table 2: Hardware Signal Descriptions (Cont.)
100-Pin
FBGA
Label
I/O
Type
Description
![](https://csdnimg.cn/release/download_crawler_static/10557253/bg14.jpg)
Hardware Signal DescriptionsBCM89820 Preliminary Data Sheet
BROADCOM CONFIDENTIAL
Broadcom
®
September 14, 2016 • 89820-DS100-R Page 20
G8 LOWPWR I
PD
CS
Low Power
Active high. If this pin is high, the device enters ultralow power-down
mode (IDDQ-LP). This mode can also be entered through software by
writing to register 1C, shadow 01100, bit 0 =1. To exit, set LOWPWR = 0
and issue a RESET
. See “Ultralow Power-Down Mode”.
Test
D4 TCK I
PU
Test Clock
JTAG serial clock.
A4 TDI I
PU
Test Data Input
JTAG serial data input.
A5 TDO O, D Test Data Output
JTAG serial data output.
A9 TMS I
PU
Test Mode Select
JTAG mode select input.
H10 TRST
I
PU
CS
JTAG Reset
Active low. Resets the JTAG controller. This signal must be pulled low
during normal operation.
G4
F4
TEST2
TEST3
I
PD
CS
Test Mode Enables
Active high. These pins must always be pulled low during normal
operation. These pins are used by Broadcom for test purposes only.
When TEST3/TEST2 = 01, the device enters a test mode where JTAG
operations can be executed.
RDAC Bias
J1 RDAC B DAC Bias Resistor
Adjusts the reference current of the transmitter digital to analog converter.
A 1.24 k ±1% resistor is connected between the RDAC pin and GND.
Power
D8, E9,
D5, E1
OVDD PWR 2.5V or 3.3V for the digital I/O pads. When 2.5V is selected, RESET
,
MDIO, and LED pins are not 3.3V tolerant.
D7, E7,
F5, G5
DVDD PWR 1.2V power for digital core.
J5, J6 AVDDL PWR 1.2V power for analog core.
J4, J10 AVDD PWR 3.3V power for analog core.
K2 PLLVDD PWR 1.2V PLL Supply to the AFE PLL
Table 2: Hardware Signal Descriptions (Cont.)
100-Pin
FBGA
Label
I/O
Type
Description
Ferrite Bead
1.2V
PLLVDD
0.1 uF
10 uF
+
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