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首页IEEE 50G以太网标准:MAC与物理层参数及管理规定
IEEE 50G以太网标准:MAC与物理层参数及管理规定
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IEEE 50G以太网规范(IEEEStandard for Ethernet Amendment 3)是IEEE Computer Society赞助的一项重要标准,于2018年12月5日批准,旨在更新和扩展现有的以太网标准,支持更高的数据传输速率。该标准主要包括三个方面:媒体访问控制(Media Access Control, MAC)参数、物理层(Physical Layer)参数以及管理参数,特别关注50 Gb/s、100 Gb/s 和 200 Gb/s 的操作。
首先,MAC参数部分是协议的核心组成部分,它定义了在50G以太网环境中数据包如何在多条链路之间进行有效的竞争访问和传输。新的MAC协议可能包括更高效的帧格式、错误检测和纠正机制,以确保在高带宽下网络的可靠性和效率。
物理层参数则着重于提供与这些高速数据传输相匹配的连接技术。这可能涵盖了新的光纤技术和接口规范,比如铜缆或光缆的信号处理方法,以及支持短距离和长距离传输的不同信道编码和调制技术。为了支持这些速度,可能需要改进信号处理算法和物理层拓扑设计,以最小化信号衰减和干扰。
管理参数部分涉及网络监控、配置和维护功能的升级。随着速率的提升,对网络性能的实时监控和故障诊断变得更加关键。新的管理协议可能包括自动化工具,以便在大规模网络中有效管理和优化50G以太网的运行,同时提高服务质量(QoS)和安全性。
IEEE 802.3cd标准是在IEEE 802.3基础标准(IEEE Std 802.3™-2018)的基础上进行修订的,后者之前已被IEEE 802.3cb™-2018和IEEE 802.3bt™-2018标准修正。这表明该新标准是在不断演进的技术环境中,对现有标准的进一步增强,以适应云计算、大数据和物联网等应用对高速网络的需求。
版权方面,所有权利归IEEE所有,未经许可不得复制或使用。标准的发布日期为2019年2月15日,出版在美国。这个规范对于工程师、网络管理员和硬件制造商来说,是推动未来网络技术发展的重要参考文档,确保了50G以太网在实际应用中的互操作性和兼容性。
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Copyright © 2019 IEEE. All rights reserved.
45.2.3.15.4 BASE-R and MultiGBASE-T PCS high BER (3.32.1) ..................................... 75
45.2.3.15.5 BASE-R and MultiGBASE-T PCS block lock (3.32.0) .................................... 75
45.2.3.16 BASE-R and MultiGBASE-T PCS status 2 register (Register 3.33) ......................... 75
45.2.3.16.1 Latched block lock (3.33.15) ............................................................................. 75
45.2.3.16.2 Latched high BER (3.33.14) .............................................................................. 75
45.2.3.16.3 BER (3.33.13:8)................................................................................................. 76
45.2.3.16.4 Errored blocks (3.33.7:0) ................................................................................... 76
45.2.3.19 BASE-R PCS test-pattern control register (Register 3.42)......................................... 76
45.2.7 Auto-Negotiation registers..................................................................................................... 76
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)...................................... 76
45.2.7.12.3 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9,
7.48.10, 7.48.11, 7.48.12, 7.48.13, 7.48.14, 7.48.15, 7.49.0, 7.49.1,
7.49.2) ............................................................................................................. 76
45.2.7.12a Backplane Ethernet, BASE-R copper status 2 (Register 7.49) ................................. 77
45.2.7.12a.1 Negotiated Port Type ....................................................................................... 77
69. Introduction to Ethernet operation over electrical backplanes ............................................................... 78
69.1 Overview......................................................................................................................................... 78
69.1.1 Scope...................................................................................................................................... 78
69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model................................... 78
69.2 Summary of Backplane Ethernet Sublayers ................................................................................... 80
69.2.1 Reconciliation sublayer and media independent interfaces................................................... 80
69.2.3 Physical Layer signaling systems .......................................................................................... 80
69.3 Delay constraints............................................................................................................................. 82
69.5 Protocol implementation conformance statement (PICS) proforma............................................... 82
73. Auto-Negotiation for backplane and copper cable assembly ................................................................. 83
73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model .................... 83
73.5 DME transmission .......................................................................................................................... 83
73.5.1 DME electrical specifications................................................................................................ 83
73.6 Link codeword encoding ................................................................................................................ 84
73.6.4 Technology Ability Field....................................................................................................... 84
73.7 Receive function requirements ....................................................................................................... 85
73.7.6 Priority Resolution function................................................................................................... 85
73.10 State diagrams and variable definitions ........................................................................................ 86
73.10.1 State diagram variables........................................................................................................ 86
73.10.2 State diagram timers ............................................................................................................ 87
78. Energy-Efficient Ethernet (EEE) ............................................................................................................ 88
78.1 Overview......................................................................................................................................... 88
78.1.4 PHY types optionally supporting EEE .................................................................................. 88
78.5 Communication link access latency................................................................................................ 89
80. Introduction to 40 Gb/s and 100 Gb/s networks ..................................................................................... 90
80.1 Overview......................................................................................................................................... 90
80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model........ 90
80.1.4 Nomenclature......................................................................................................................... 91
80.1.5 Physical Layer signaling systems .......................................................................................... 92
80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers ......................................................... 93
80.2.2 Physical Coding Sublayer (PCS) ........................................................................................... 93
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Copyright © 2019 IEEE. All rights reserved.
80.2.3 Forward Error Correction (FEC) sublayers ........................................................................... 93
80.2.4 Physical Medium Attachment (PMA) sublayer..................................................................... 94
80.2.5 Physical Medium Dependent (PMD) sublayer ...................................................................... 94
80.2.6 Auto-Negotiation ................................................................................................................... 94
80.4 Delay constraints............................................................................................................................. 95
80.5 Skew constraints ............................................................................................................................. 96
80.7 Protocol implementation conformance statement (PICS) proforma............................................... 99
82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R ....................... 100
82.6 Auto-Negotiation .......................................................................................................................... 100
82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical
Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R.......................... 100
82.7.4 PICS proforma tables for PCS, type 40GBASE-R and 100GBASE-R ............................... 100
82.7.4.11 Auto-Negotiation for Backplane Ethernet functions ................................................ 100
90. Ethernet support for time synchronization protocols............................................................................ 101
90.1 Introduction................................................................................................................................... 101
91. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs .................... 102
91.3 PMA compatibility ....................................................................................................................... 102
91.5 Functions within the RS-FEC sublayer ........................................................................................ 102
91.5.2 Transmit function................................................................................................................. 102
91.5.2.6 Alignment marker mapping and insertion .................................................................. 102
91.5.2.7 Reed-Solomon encoder............................................................................................... 102
91.5.3 Receive function .................................................................................................................. 103
91.5.3.3 Reed-Solomon decoder............................................................................................... 103
91.5.3.3.1 FEC Degraded SER (optional) .......................................................................... 103
91.6 RS-FEC MDIO function mapping................................................................................................ 104
91.6.2a four_lane_pmd ................................................................................................................... 104
91.6.2b FEC_degraded_SER_enable.............................................................................................. 104
91.6.2c FEC_degraded_SER_activate_threshold ........................................................................... 105
91.6.2d FEC_degraded_SER_deactivate_threshold ....................................................................... 105
91.6.2e FEC_degraded_SER_interval ............................................................................................ 105
91.6.5a FEC_degraded_SER_ability .............................................................................................. 105
91.6.5b FEC_degraded_SER .......................................................................................................... 105
91.7 Protocol implementation conformance statement (PICS) proforma for Clause 91, Reed-
Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs.................. 105
91.7.3 Major capabilities/options.................................................................................................... 105
91.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer
for 100GBASE-R PHYs ................................................................................................... 106
91.7.4.1 Transmit function........................................................................................................ 106
91.7.4.2 Receive function ......................................................................................................... 106
116. Introduction to 200 Gb/s and 400 Gb/s networks ............................................................................... 108
116.1 Overview..................................................................................................................................... 108
116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference
model ................................................................................................................................ 108
116.1.3 Nomenclature..................................................................................................................... 108
116.1.4 Physical Layer signaling systems ...................................................................................... 108
116.2 Summary of 200 Gigabit and 400 Gigabit Ethernet sublayers ................................................... 110
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Copyright © 2019 IEEE. All rights reserved.
116.2.5 Physical Medium Dependent (PMD) sublayer .................................................................. 110
116.4 Delay constraints......................................................................................................................... 110
119. Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R ................... 111
119.5a Auto-Negotiation ...................................................................................................................... 111
119.6 Protocol implementation conformance statement (PICS) proforma for Clause 119, Physical
Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R........................ 111
119.6.4 PICS proforma tables for Physical Coding Sublayer (PCS) 64B/66B, type
200GBASE-R and 400GBASE-R .................................................................................... 111
119.6.4.12 Auto-Negotiation for Backplane Ethernet functions ............................................. 111
120. Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R.................. 112
120.5 Functions within the PMA.......................................................................................................... 112
120.5.7 PAM4 Encoding Gray mapping for PAM4 encoded lanes................................................ 112
120.5.7.1 Gray mapping for PAM4 encoded lanes................................................................... 112
120.5.7.2 Precoding for PAM4 encoded lanes ......................................................................... 112
120.6 PMA MDIO function mapping................................................................................................... 112
120.7 Protocol implementation conformance statement (PICS) proforma for Clause 120, Physical
Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R ...................... 113
120.7.7 Encoding ............................................................................................................................ 113
131. Introduction to 50 Gb/s networks ....................................................................................................... 114
131.1 Overview..................................................................................................................................... 114
131.1.1 Scope.................................................................................................................................. 114
131.1.2 Relationship of 50 Gigabit Ethernet to the ISO OSI reference model............................... 114
131.1.3 Nomenclature..................................................................................................................... 114
131.1.4 Physical Layer signaling systems ...................................................................................... 116
131.2 Summary of 50 Gigabit Ethernet sublayers................................................................................ 117
131.2.1 Reconciliation Sublayer (RS) and Media Independent Interface (50GMII)...................... 117
131.2.2 Physical Coding Sublayer (PCS) ....................................................................................... 117
131.2.3 Forward Error Correction (FEC) sublayer......................................................................... 117
131.2.4 Physical Medium Attachment (PMA) sublayer................................................................. 117
131.2.5 Physical Medium Dependent (PMD) sublayer .................................................................. 117
131.2.6 Management interface (MDIO/MDC) ............................................................................... 117
131.2.7 Management....................................................................................................................... 118
131.3 Service interface specification method and notation .................................................................. 118
131.3.1 Inter-sublayer service interface.......................................................................................... 118
131.3.2 Instances of the Inter-sublayer service interface................................................................ 118
131.3.3 Semantics of inter-sublayer service interface primitives................................................... 118
131.4 Delay constraints......................................................................................................................... 120
131.5 Skew constraints ......................................................................................................................... 120
131.6 State diagrams............................................................................................................................. 123
131.7 Protocol implementation conformance statement (PICS) proforma........................................... 123
132. Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s operation ... 124
132.1 Overview..................................................................................................................................... 124
132.1.1 Summary of major concepts .............................................................................................. 124
132.1.2 Application......................................................................................................................... 124
132.1.3 Rate of operation................................................................................................................ 124
132.1.4 Delay constraints................................................................................................................ 125
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Copyright © 2019 IEEE. All rights reserved.
132.1.5 Allocation of functions ...................................................................................................... 126
132.1.6 50GMII structure ............................................................................................................... 126
132.1.7 Mapping of 50GMII signals to PLS service primitives..................................................... 126
132.2 50GMII data stream .................................................................................................................... 126
132.3 50GMII functional specifications ............................................................................................... 126
132.4 LPI assertion and detection......................................................................................................... 126
132.5 Protocol implementation conformance statement (PICS) proforma for Clause 132,
Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s
operation ................................................................................................................................... 127
132.5.1 Introduction........................................................................................................................ 127
132.5.2 Identification...................................................................................................................... 127
132.5.2.1 Implementation identification................................................................................... 127
132.5.2.2 Protocol summary..................................................................................................... 127
132.5.2.3 Major capabilities/options ........................................................................................ 128
132.5.3 PICS proforma tables for Reconciliation Sublayer (RS) and Media Independent
Interface (50GMII) for 50 Gb/s operation ........................................................................ 128
132.5.3.1 General ..................................................................................................................... 128
132.5.3.2 Mapping of PLS service primitives .......................................................................... 128
133. Physical Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R .................................................... 129
133.1 Overview..................................................................................................................................... 129
133.1.1 Scope.................................................................................................................................. 129
133.1.2 Relationship of 50GBASE-R to other standards ............................................................... 129
133.1.3 Summary of 50GBASE-R sublayers ................................................................................. 129
133.1.3.1 Physical Coding Sublayer (PCS) .............................................................................. 129
133.1.4 Inter-sublayer interfaces .................................................................................................... 129
133.1.4.1 PCS service interface (50GMII) ............................................................................... 129
133.1.4.2 Forward Error Correction (FEC) or Physical Medium Attachment (PMA)
service interface ...................................................................................................... 130
133.1.5 Functional block diagram .................................................................................................. 131
133.2 Physical Coding Sublayer (PCS) ................................................................................................ 132
133.2.1 Functions within the PCS .................................................................................................. 132
133.2.2 Alignment marker insertion............................................................................................... 132
133.2.3 PCS lane deskew................................................................................................................ 133
133.2.4 Detailed functions and state diagrams ............................................................................... 133
133.3 Delay constraints......................................................................................................................... 133
133.4 Auto-Negotiation ........................................................................................................................ 133
133.5 Protocol implementation conformance statement (PICS) proforma for Clause 133, Physical
Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R......................................................... 134
133.5.1 Introduction........................................................................................................................ 134
133.5.2 Identification...................................................................................................................... 134
133.5.2.1 Implementation identification................................................................................... 134
133.5.2.2 Protocol summary..................................................................................................... 134
133.5.3 Major capabilities/options.................................................................................................. 135
133.5.4 PICS proforma tables for Physical Coding Sublayer (PCS) for 64B/66B, type
50GBASE-R ..................................................................................................................... 135
133.5.4.1 Coding rules.............................................................................................................. 135
133.5.4.2 Scrambler and Descrambler...................................................................................... 136
133.5.4.3 Deskew and Reordering............................................................................................ 136
133.5.4.4 Alignment Markers ................................................................................................... 136
133.5.4.5 Test-pattern modes.................................................................................................... 136
133.5.4.6 Bit order .................................................................................................................... 137
133.5.4.7 Management.............................................................................................................. 137
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Copyright © 2019 IEEE. All rights reserved.
133.5.4.8 State diagrams........................................................................................................... 137
133.5.4.9 Loopback ................................................................................................................. 138
133.5.4.10 Delay constraints..................................................................................................... 138
133.5.4.11 Auto-Negotiation for Backplane Ethernet functions ............................................. 138
134. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 50GBASE-R PHYs .................... 139
134.1 Overview..................................................................................................................................... 139
134.1.1 Scope.................................................................................................................................. 139
134.1.2 Position of RS-FEC in the 50GBASE-R sublayers ........................................................... 139
134.2 FEC service interface.................................................................................................................. 139
134.3 PMA compatibility ..................................................................................................................... 140
134.4 Delay constraints......................................................................................................................... 141
134.5 Functions within the RS-FEC sublayer ...................................................................................... 141
134.5.1 Functional block diagram .................................................................................................. 141
134.5.2 Transmit function............................................................................................................... 141
134.5.2.1 PCS Lane block synchronization.............................................................................. 141
134.5.2.2 PCS Alignment lock and deskew.............................................................................. 141
134.5.2.3 PCS Lane reorder...................................................................................................... 141
134.5.2.4 Alignment marker removal....................................................................................... 141
134.5.2.5 64B/66B to 256B/257B transcoder........................................................................... 142
134.5.2.6 Alignment marker mapping and insertion ................................................................ 143
134.5.2.7 Reed-Solomon encoder............................................................................................. 144
134.5.2.8 Symbol distribution................................................................................................... 144
134.5.2.9 Transmit bit ordering ................................................................................................ 144
134.5.3 Receive function ................................................................................................................ 144
134.5.3.1 Alignment lock and deskew...................................................................................... 144
134.5.3.2 FEC Lane reorder...................................................................................................... 146
134.5.3.3 Reed-Solomon decoder............................................................................................. 146
134.5.3.3.1 FEC Error indication bypass (optional) ........................................................... 146
134.5.3.3.2 FEC Degraded SER (optional) ........................................................................ 147
134.5.3.4 Alignment marker removal....................................................................................... 147
134.5.3.5 256B/257B to 64B/66B transcoder........................................................................... 147
134.5.3.6 Block distribution ..................................................................................................... 147
134.5.3.7 Alignment marker mapping and insertion ................................................................ 147
134.5.3.8 Receive bit ordering.................................................................................................. 148
134.5.4 Detailed functions and state diagrams ............................................................................... 148
134.5.4.1 State diagram conventions ........................................................................................ 148
134.5.4.2 State variables ........................................................................................................... 150
134.5.4.2.1 Variables .......................................................................................................... 150
134.5.4.2.2 Functions.......................................................................................................... 150
134.5.4.2.3 Counters........................................................................................................... 150
134.5.4.3 State diagrams........................................................................................................... 150
134.6 RS-FEC MDIO function mapping.............................................................................................. 151
134.6.1 FEC_bypass_indication_enable......................................................................................... 152
134.6.2 FEC_degraded_SER_enable.............................................................................................. 152
134.6.3 FEC_degraded_SER_activate_threshold........................................................................... 152
134.6.4 FEC_degraded_SER_deactivate_threshold ....................................................................... 152
134.6.5 FEC_degraded_SER_interval ............................................................................................ 152
134.6.6 FEC_bypass_indication_ability ......................................................................................... 152
134.6.7 hi_ser.................................................................................................................................. 153
134.6.8 FEC_degraded_SER_ability.............................................................................................. 153
134.6.9 FEC_degraded_SER .......................................................................................................... 153
134.6.10 fec_optional_states........................................................................................................... 153
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