TI TPS65983B：USB-C和PD控制器，高速Mux解决方案

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TI-TPS65983B是一款高性能的USB Type-C和USB Power Delivery (USB PD) 控制器，专为现代电子设备设计，旨在实现高效、灵活的电源管理和连接功能。该文档详细介绍了产品的关键特性： 1. **USB PD控制器功能**： - 支持PD2.0和PD3.0协议，满足不同版本的USB Power Delivery标准，确保兼容性。 - 快速角色交换能力，允许设备在主机、设备或双向供电/受电模式之间切换。 - 包含双相标记编码/解码（BMC），用于数据通信的准确传输。 - 提供物理层和策略引擎，确保信号完整性与电源管理的智能化。 - 可配置为自举控制模式，适应多种应用场景，同时支持主机控制。 2. **USB Type-C接口**： - 符合USB Type-C规范，实现对电缆方向和角色的精确检测，确保连接安全。 - 能够自动分配CC (Communications Channel) 和 VCONN 引脚，提供灵活的电源管理。 - 具备多种预设电流选项，包括默认值、1.5A和3A，以适应不同负载需求。 3. **端口电源开关**： - 内置5V/3A的Type-C电源开关，控制VBUS电压，保护电路不受过压损害。 - 提供5V到20V/3A双向开关，适用于USB PD电源的VBUS，支持双向供电和接收。 - 这些开关功能有助于优化电池充电和设备供电效率。 4. **电压范围**： - 该控制器工作范围广泛，支持5V到20V的输入电压，确保在不同电源条件下稳定运行。 5. **版权和注意事项**： - 文档提供的中文版本仅供参考，建议用户在进行设计时参考最新的英文版(SLVSDM6)以获取最准确和全面的信息。 - TI公司强调了其网站www.ti.com作为获取官方英文资料的首选，且翻译可能存在误差，因此设计者应以英文数据表为准。综上，TPS65983B是一款功能强大的USB Type-C控制器，它集成了USB PD功能，适用于需要高效电源管理和高速数据传输的便携式设备，如智能手机、笔记本电脑和移动电源等。

TPS65983B

ZHCSFL8B –OCTOBER 2016–REVISED JUNE 2018

www.ti.com.cn

Port Power Switch Characteristics (continued)

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

(5) Limit the resistance from the HV_GATE1/2 pins to the external FET gate pins to < 1Ω to provide adequate response time to short circuit

events.

IHVEXT_ACC

PP_EXT current sense accuracy (excluding

RSENSE accuracy)

I = 100 mA , RSENSE = 10 mΩ

Reverse current blocking disabled

3.5 5 6.5 A/V

I = 200 mA, RSENSE = 10 mΩ 4 5 6 A/V

I = 500 mA, RSENSE = 10 mΩ 4.4 5 5.6 A/V

I ≥ 1 A, RSENSE = 10 mΩ 4.5 5 5.5 A/V

IPP5V_ACC

(4)

PP_5V0 current sense accuracy

I = 100 mA Reverse current

blocking disabled

1.95 3 4.05 A/V

I = 200 mA 2.4 3 3.6 A/V

I = 500 mA 2.64 3 3.36 A/V

I ≥ 1 A 2.7 3 3.3 A/V

IPPCBL_ACC PP_CABLE current sense accuracy

I = 100 mA - 1 - A/V

I = 200 mA - 1 - A/V

I = 500 mA - 1 - A/V

IGATEEXT

(5)

External Gate Drive Current on HV_GATE1

and HV_GATE2

4 5 6 μA

VGSEXT VGS voltage driving external FETs 4.5 7.5 V

TON_HV

PP_HV path turn on time from enable to VBUS

= 95% of PP_HV voltage

Configured as a source or as a

sink with soft start disabled.

PP_HV = 20 V, CVBUS = 10 μF,

ILOAD = 100 mA

8 ms

TON_5V

PP_5V0 path turn on time from enable to

VBUS = 95% of PP_5V0 voltage

Configured as a source or as a

sink with soft start disabled.

PP_5V0 = 5 V, CVBUS = 10 μF,

ILOAD = 100 mA

2.5 ms

TON_CC

PP_CABLE path turn on time from enable to

C_CCn = 95% of the PP_CABLE voltage

PP_CABLE = 5 V, C_CCn = 500

nF, ILOAD = 100 mA

2 ms

ISS Soft start charging current 5.5 7 8.5 μA

RSS_DIS Soft start discharge resistance 0.6 1 1.4 kΩ

VTHSS Soft start complete threshold 1.35 1.5 1.65 V

TSSDONE Soft start complete time CSS = 470 nF 68.3 99 129.7 ms

VREVPHV

Reverse current blocking voltage threshold for

PP_HV switch

2 6 10 mV

VREVPEXT

Reverse Current Blocking voltage Threshold for

PP_EXT external switches

2 6 10 mV

VREV5V0

Reverse current blocking voltage threshold for

PP_5V0 switches

2 6 10 mV

VHVDISPD

Voltage threshold above VIN at which the

pulldown RHVDISPD on VBUS will disable

during a transition from PHV to 5V0

45 200 250 mV

VSAFE0V

Voltage that is a safe 0 V per USB-PD

Specifications

0 0.8 V

TSAFE0V Voltage transition time to VSAFE0V 650 ms

VSO_HV

Voltage on PP_HV or PP_HVEXT above which

the PP_HV or PP_EXT to PP_5V0 transition on

VBUS will meet transition requirements

9.9 V

SRPOS

Maximum slew rate for positive voltage

transitions

0.03 V/μs

SRNEG

Maximum slew rate for negative voltage

transitions

–0.03 V/μs

TSTABLE

EN to stable time for both positive and negative

voltage transitions

275 ms

VSRCVALID

Supply Output Tolerance beyond VSRCNEW

during time TSTABLE

–0.5 0.5 V

VSRCNEW Supply Output Tolerance –5 5 %

RFRSTX Fast Role Swap request pulldown resistance 5 Ω

TFRSTX Fast Role Swap request transmit duration 60 120 μs

TPS65983B

www.ti.com.cn

ZHCSFL8B –OCTOBER 2016–REVISED JUNE 2018

Port Power Switch Characteristics (continued)

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS

(1)

MIN TYP MAX UNIT

VFRSDETECT

Fast Role Swap request voltage detection

threshold

490 520 550 mV

TFRSRX Fast Role Swap request detection time 30 50 μs

(1) All RON specified maximums are the maximum of either of the switches in a pair. All ROND specified maximums are the maximum

difference between the two switches in a pair. ROND does not add to RON.

7.12 Port Data Multiplexer Switching and Timing Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SWD MULTIPLEXER PATH

(1)

SWD_RON_U

On resistance of SWD_DATA/CLK to

C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 35 55

= 1 V, I

= 20 mA 30 46

SWD_ROND_U

On resistance difference between P and N paths of

SWD_DATA/CLK to C_USB_ TP/TN/BP/BN

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

SWD_RON_S On resistance of SWD_DATA/CLK to C_SBU1/2

= 3.3 V, I

= 20 mA 26 42

= = 1 V, I

= 20 mA 24 37

SWD_ROND_S

On resistance difference between P and N paths of

SWD_DATA/CLK to C_SBU1/2

= 1V to 3.3 V, I

= 20 mA –1.5 1.5 Ω

SWD_TON Switch on time from enable of SWD path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

SWD_TOFF Switch off time from disable of SWD path

Time from disable bit at charge

pump steady state

500 ns

SWD_BW 3 dB bandwidth of SWD path C

= 10 pF 200 MHz

DEBUG1/2 MULTIPLEXER PATH

(1)

DB1_RON_U On resistance DEBUG1/2 to C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 14 26

= 1 V, I

= 20 mA 10 17

DB1_ROND_U

On resistance difference between P and N paths of

DEBUG1/2 to C_USB_TP/TN/BP/BN

= 1 V to 3.3 V, I

= 20 mA –2.5 2.5 Ω

DB1_RON_S On resistance of DEBUG1/2 to C_SBU1/2

= 3.3 V, I

= 20 mA 9.5 17

= 1 V, I

= 20 mA 6.5 12

DB1_ROND_S

On resistance difference between P and N paths of Debug

path DEBUG1/2 to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.5 0.5 Ω

DB1_TON Switch on time from enable of DEBUG path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

DB1_TOFF Switch off time from disable of DEBUG path

Time from disable bit at charge

pump steady state

500 ns

DB1_BW 3dB bandwidth of DEBUG path C

= 10 pF 200 MHz

DEBUG3/4 MULTIPLEXER PATH

(1)

DB3_RON_U On resistance of DEBUG3/4 to C_USB_TP/TN/BP/BN

= 3.3 V, I

= 20 mA 14 24

= 1 V, I

= 20 mA 9 17

DB3_ROND_U

On resistance difference between P and N paths of

DEBUG3/4 to C_USB_ TP/TN/BP/BN

= 1 V to 3.3V, I

= 20 mA –1.5 1.5 Ω

DB3_RON_S On resistance of DEBUG3/4 to C_SBU1/2

= 3.3 V, I

= 20 mA 9.5 18

= 1 V, I

= 20 mA 6.5 12

DB3_ROND_S

On resistance difference between P and N paths of

DEBUG3/4 to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.15 0.15 Ω

DB3_TON Switch on time from enable of DEBUG3/4 path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

TPS65983B

ZHCSFL8B –OCTOBER 2016–REVISED JUNE 2018

www.ti.com.cn

Port Data Multiplexer Switching and Timing Characteristics (continued)

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) The UART switch path connects from the UART buffers to the port pins. See Input/Output (I/O) Requirements and Characteristics for

buffer specifications.

(3) See Port Data Multiplexer USB Endpoint Requirements and Characteristics for the USB_EP specifications.

DB3_TOFF Switch off time from disable of DEBUG3/4 path

Time from disable bit at charge

pump steady state

500 ns

DB3_BW 3dB bandwidth of DEBUG3/4 path C

= 10 pF 200 MHz

LSX_R2P/P2R MULTIPLEXER PATH

(1)

LSX_RON On resistance of LSX_P2R/R2P to C_SBU1/2

= 3.3 V, I

= 20 mA 8.5 17

= 1 V, I

= 20 mA 5.5 11

LSX_ROND

On resistance difference between P and N paths of LSX

path

= 1 V to 3.3 V, I

= 20 mA –0.3 0.3 Ω

LSX_TON Switch on time from enable of LSX path

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

LSX_TOFF Switch off time from disable of LSX path

Time from disable bit at charge

pump steady state

500 ns

LSX_BW 3dB bandwidth of LSX path C

= 10 pF 200 MHz

AUX MULTIPLEXER PATH

(1)

AUX_RON On resistance of AUX_P/N to C_SBU1/2

= 3.3 V, I

= 20 mA 3.5 7

= 1 V, I

= 20 mA 2.5 5

AUX_ROND

On resistance difference between P and N paths of

AUX_P/N to C_SBU1/2

= 1 V to 3.3 V, I

= 20 mA –0.25 0.25 Ω

AUX_TON Switch on time from enable of AUX_P/N to C_SBU1/2

Time from enable bit with charge

pump off

150

μs

Time from enable bit at charge

pump steady state

AUX_TOFF Switch off time from disable of AUX_P/N to C_SBU1/2

Time from disable bit at charge

pump steady state

500 ns

AUX_BW 3dB bandwidth of AUX_P/N to C_SBU1/2 path C

= 10 pF 200 MHz

UART MULTIPLEXER PATH (2

Stage Only)

(1)(2)

UART_RON

On resistance of UART buffers to C_USB_TP/TN/BP/BN or

C_SBU1/2

= 3.3 V, I

= 20 mA 3.1 12 Ω

UART_TON

Switch on time from enable of UART buffer

C_USB_TP/TN/BP/BN or C_SBU1/2 path

Time from enable bit with charge

pump off

150

µs

Time from enable bit at charge

pump steady state

UART_TOFF Switch off time from disable of UART buffer path

Time from disable bit at charge

pump steady state

500 ns

UART_BW 3dB bandwidth of UART buffer path C

= 10 pF 200 MHz

USB_RP MULTIPLEXER PATH

(1)(3)

USB_RON On resistance of USB_RP to C_USB_TP/TN/BP/BN

= 3 V, I

= 20 mA 4.5 10

= 400 mV, I

= 20 mA 3 7

USB_ROND

On resistance difference between P and N paths of

USB_RP to C_USB_TP/TN/BP/BN

= 0.4 V to 3 V, I

= 20 mA –0.15 0.15 Ω

USB_TON Switch on time from enable of USB USB_RP path

Time from enable bit with charge

pump off

150

µs

Time from enable bit at charge

pump steady state

USB_TOFF Switch off time from disable of USB_RP path

Time from disable bit at charge

pump steady state

500 ns

USB_BW 3dB bandwidth of USB_RP path C

= 10 pF 850 MHz

USB_ISO Off Isolation of USB_RP path

= 50 Ω, V

= 800 mV, f = 240

MHz

–19 dB

USB_XTLK Channel to Channel crosstalk of USB_RP path R

= 50 Ω, f = 240 MHz –26 dB

TPS65983B

www.ti.com.cn

ZHCSFL8B –OCTOBER 2016–REVISED JUNE 2018

Port Data Multiplexer Switching and Timing Characteristics (continued)

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C_SBU1/2 OUTPUT

R_SBU_OPEN Resistance of the open C_SBU1/2 paths V

= 0 V to LDO_3V3 1 MΩ

R_USB_OPEN Resistance of the open C_USB_T/B/P/N paths V

= 0 V to LDO_3V3 1 MΩ

(1) The TCLMP_PRT time includes the time through the digital synchronizers. When the clock speed is reduced, the signal assertion time

may be longer.

7.13 Port Data Multiplexer Clamp Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCLMP_IND Clamp Voltage triggering indicator to Digital Core 3.8 3.95 4.1 V

ICLMP_IND Clamp Current at VCLMP_IND 10 250 μA

TCLMP_PRT

(1)

Time from clamp current crossing ICLMP_IND to

interrupt signal assertion

I ≥ ICLMP_IND rising 0 4 μs

ICLMP USB_EP and USB_RP Port Clamp Current

V = LDO_3V3 250 nA

V = VCLMP_IND + 500 mV 3.5 15 mA

7.14 Port Data Multiplexer SBU Detection Requirements

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH_PORT Port switch detect input high voltage LDO_3V3 = 3.3 V 2.0 v

VIL_PORT Port switch detect input low voltage LDO_3V3 = 3.3 V 0.8 V

7.15 Port Data Multiplexer Signal Monitoring Pullup and Pulldown Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RPU05 500-Ω pullup and down resistance LDO_3V3 = 3.3 V 350 500 650 Ω

RTPU5 5-kΩ pullup and down resistance LDO_3V3 = 3.3 V 3.5 5 6.5 kΩ

RPU100 100-kΩ pullup and down resistance LDO_3V3 = 3.3 V 70 100 130 kΩ

(1) The USB Endpoint PHY is functional across the entire VIN_3V3 operating range, but parameter values are only verified by design for

VIN_3V3 ≥ 3.135 V

7.16 Port Data Multiplexer USB Endpoint Requirements and Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TRANSMITTER

(1)

T_RISE_EP Rising transition time Low-speed (1.5 Mbps) data rate only 75 300 ns

T_FALL_EP Falling transition time Low-speed (1.5 Mbps) data rate only 75 300 ns

T_RRM_EP Rise and fall time matching Low-speed (1.5 Mbps) data rate only –20% 25%

V_XOVER_EP Output crossover voltage 1.3 2 V

RS_EP

Source resistance of driver including 2nd Stage Port

Data Multiplexer

34 Ω

DIFFERENTIAL RECEIVER

(1)

VOS_DIFF_EP Input offset –100 100 mV

VIN_CM_EP Common Mode Range 0.8 2.5 V

RPU_EP D– Bias Resistance Receiving 1.425 1.575 kΩ

SINGLE ENDED RECEIVER

(1)

VTH_SE_EP Single ended threshold Signal rising/falling 0.8 2 V

VHYS_SE_EP Single ended threshold hysteresis Signal falling 200 mV

TPS65983B

ZHCSFL8B –OCTOBER 2016–REVISED JUNE 2018

www.ti.com.cn

7.17 Port Data Multiplexer BC1.2 Detection Requirements and Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DATA CONTACT DETECT

IDP_SRC DCD Source Current LDO_3V3 = 3.3 V 7 10 13 μA

RDM_DWN DCD pulldown resistance 14.25 20 24.8 kΩ

VLGC_HI Threshold for no connection

VC_USB_TP/BP ≥

VLGC_HILDO_3V3 = 3.3 V

LDO_3V3 = 3.3 V

2 V

VLGC_LO Threshold for connection

VC_USB_TP/BP ≤ VLGC_LO

LDO_3V3 = 3.3 V

0.8 V

PRIMARY AND SECONDARY DETECT

VDX_SRC Source voltage 0.55 0.6 0.65 V

VDX_RSRC Total series resistance due to Port Data Multiplexer VDX_SRC = 0.65 V 65 Ω

VDX_ILIM VDX_SRC current limit 250 400 μA

IDX_SNK Sink Current VC_USB_TN/BN ≥ 250 mV 25 75 125 μA

7.18 Analog-to-Digital Converter (ADC) Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

RES_ADC ADC resolution 10 bits

F_ADC ADC clock frequency 1.477 1.5 1.523 MHz

T_ENA ADC enable time 42.14 43 43.86 μs

T_SAMPLEA ADC input sample time 10.5 10.67 10.9 μs

T_CONVERTA ADC conversion time 7.88 8 8.12 μs

T_INTA ADC interrupt time 1.31 1.33 1.35 μs

LSB Least significant bit 1.152 1.17 1.188 mV

DNL Differential non-linearity –0.65 0.65 LSB

INL Integral non-linearity –1.2 1.2 LSB

GAIN_ERR

Gain error (divider) –1.5% 1.5%

Gain error (no divider) –1 1

VOS_ERR Buffer offset error –10 10 mV

THERM_ACC Thermal sense accuracy –8 8 °C

THERM_GAIN Thermal slope 3.095 mV/°C

THERM_V0 Zero degree voltage 0.823 V

7.19 Input/Output (I/O) Requirements and Characteristics

Recommended operating conditions; T

= –10 to +85°C unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SPI

SPI_VIH High-level input voltage LDO_3V3 = 3.3 V 2 V

SPI_VIL Low-level input voltage LDO_3V3 = 3.3 V 0.8 V

SPI_HYS Input hysteresis voltage LDO_3V3 = 3.3 V 0.2 V

SPI_ILKG Leakage current Output is Hi-Z, V

= 0 to LDO_3V3 –1 1 μA

SPI_VOH SPI output high voltage

= –8 mA, LDO_3V3=3.3 V 2.9 V

= –15 mA, LDO_3V3=3.3 V 2.5

SPI_VOL SPI output low voltage

= 10 mA 0.4 V

= 20 mA 0.8

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