Xicor X84161 高速低功耗EEPROM技术规格

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"X84161是一款高性能的MPS™EEPROM，具有高速数据传输、低功耗和高可靠性等特点。" X84161是Xicor公司生产的一款微端口保存（µPortSaver）EEPROM，适用于微处理器和微控制器的直接接口。这款芯片的主要特点是其高效能和低能耗设计，使其在各种应用中成为理想的选择。首先，X84161提供了高达10MHz的数据传输速率，这意味着它能在短时间内处理大量数据，极大地提高了系统的运行效率。此外，它的读取访问时间仅为25ns，这使得数据读取非常快速，满足了对实时性有较高要求的系统需求。在接口设计上，X84161可以直接与微处理器和微控制器对接，无需额外的I/O端口或接口逻辑。这简化了系统架构，减少了硬件复杂性和成本，并且省去了并行到串行转换器的需求，降低了系统的整体体积。在电源管理方面，X84161支持宽电压范围，包括1.8V至3.6V、2.5V至5.5V以及5V±10%的版本。在待机状态下，其电流消耗小于1µA，而在工作时，电流消耗也不超过1mA，显著降低了系统的能耗。该芯片还具备字节写入或页面写入能力，支持32字节的页面写模式。非挥发性写入周期时间典型值为2毫秒，意味着即使在断电后，写入的数据也能被安全地保存。在可靠性方面，X84161的设计十分坚固，可承受100,000次的耐久性循环，确保了长时间稳定的工作。并且，它保证了数据保留时间为100年，用户可以放心地依赖其长期存储关键信息。 X84161的出现，无论是作为字宽数据内存的替代品还是替代串行内存，都提供了串行内存的优势，如低成本、低功耗、低压操作和紧凑的封装。由于其小尺寸和低能耗，它特别适合在空间有限和能源敏感的应用场景中使用。 X84161是一种高效、低功耗、高可靠性的微端口保存EEPROM，适合在需要高速数据传输、低功耗和紧凑型设计的嵌入式系统中使用。无论是在工业控制、汽车电子、通信设备还是消费电子产品中，X84161都能提供出色的表现。

X84161/641/129

Write Sequence

A nonvolatile write sequence consists of sending a reset

sequence, a 16-bit address, up to 32 bytes of data, and

then a special “start nonvolatile write cycle” command

sequence.

The reset sequence is issued ﬁrst (as described in the

Reset Sequence section) to set an internal write enable

latch. The address is written serially by issuing 16

separate write cycles (WE

and CE LOW, OE HIGH) to

the part without any read cycles between the writes. The

address is sent serially, most signiﬁcant bit ﬁrst, on the

l/O pin. Up to 32 bytes of data are written by issuing a

multiple of 8 write cycles. Again, no read cycles are

allowed between writes.

The nonvolatile write cycle is initiated by issuing a special

read/write “1”/read sequence. The ﬁrst read cycle ends

the page load, then the write “1” followed by a read starts

the nonvolatile write cycle. The device recognizes 32-

byte pages (e.g., beginning at addresses XXXXXX00000

for X84161).

When sending data to the part, attempts to exceed the

upper address of the page will result in the address

counter “wrapping-around” to the ﬁrst address on the

page, where data loading can continue. For this reason,

sending more than 256 consecutive data bits will result in

overwriting previous data.

A nonvolatile write cycle will not start if a partial or incom-

plete write sequence is issued. The internal write enable

latch is reset when the nonvolatile write cycle is com-

pleted and after an invalid write to prevent inadvertent

writes. Note that this sequence is fully static, with no spe-

cial timing restrictions. The processor is free to perform

other tasks on the bus whenever the chip enable pin (CE)

is HIGH.

Nonvolatile Write Status

The status of a nonvolatile write cycle can be determined

at any time by simply reading the state of the l/O pin on

the device. This pin is read when OE and CE are LOW

and WE is HIGH. During a nonvolatile write cycle the l/O

pin is LOW. When the nonvolatile write cycle is complete,

the l/O pin goes HIGH. A reset sequence can also be

issued during a nonvolatile write cycle with the same

result: I/O is LOW as long as a nonvolatile write cycle is

in progress, and l/O is HIGH when the nonvolatile write

cycle is done.

Figure 2: Write Sequence

I/O (IN)

"0"

"1"

RESET LOAD ADDRESS LOAD DATA START

NONVOLATILE

WRITE

A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

I/O (OUT)

7008 FRM F05.1

WHEN ACCESSING: X84161 ARRAY: A15–A11=0

X84641 ARRAY: A15–A13=0

X84129 ARRAY: A15–A14=0

A15 A14 A13 A12 A11

A10

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