STM32F101x/C/D/E与F103x/C/D/E Revision Z ARM Cortex-M3 Errata与识别指南

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"ARM ST堪误表是ST官方发布的一份针对STM32F101xC/D/E和STM32F103xC/D/E系列芯片的错误修正文档，适用于这些高密度产品的Z版本。该文档详细列出了ARM Cortex-M3内核的特定限制，并提供了相应的故障排除和规避策略。这些芯片集成了32位Cortex-M3处理器，同时还有一个单独的错误通知（见第1节获取更多详情）。文档的核心部分首先介绍了识别这些设备的方法。设备的修订代码可以通过以下两种方式查看： 1. 在设备封装下方的销售类型标记处找到修订代码标记。 2. 查看包装盒标签上打印的内部销售类型，其最后三位数字表示修订版本。在STM32F103xC、STM32F103xD和STM32F103xE型号中，用户可以通过查阅附录A中的详细说明，了解如何根据设备上的标记确定修订代码，因为不同的封装可能有不同的标识方法。对于STM32F101xC/D/E系列，错误列表和建议的解决方案集中在可能遇到的硬件缺陷和性能问题上，包括但不限于时钟问题、功耗优化、内存访问限制等。这份文档对确保设备的稳定性和优化用户应用程序的性能至关重要，因此在设计和开发过程中，工程师应参考这份官方文档来避免因已知错误导致的问题，并采取适当的预防措施。此外，文档还强调了在处理这些设备时，需要查阅STM32F10xxx参考手册，以获得关于如何获取和解读设备修订代码的详细信息，这对于正确识别和应对特定问题至关重要。ARM ST堪误表是一个实用的资源，对于使用STM32F101xC/D/E和STM32F103xC/D/E系列芯片的开发者来说，是不可或缺的技术参考资料。"

ARM™ 32-bit Cortex

-M3 limitations Errata sheet

6/28 Doc ID 14732 Rev 6

1 ARM™ 32-bit Cortex

-M3 limitations

An errata notice of the STM32F10xxx core is available from the following web address:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.eat0420a/.

The direct link to the errata notice pdf is:

http://infocenter.arm.com/help/topic/com.arm.doc.eat0420a/Cortex-M3-Errata-r1p1-v0.2.pdf.

All the described limitations are minor and related to the revision r1p1-01rel0 of the Cortex-

M3 core. Ta bl e 3 summarizes these limitations and their implications on the behavior of

high-density STM32F10xxx devices.

1.1 Cortex-M3 limitations description for STM32F10xxx high-

density devices

Only the limitations described below have an impact, even though minor, on the

implementation of STM32F10xxx high-density devices.

All the other limitations described in the ARM errata notice (and summarized in Ta bl e 3

above) have no impact and are not related to the implementation of STM32F10xxx high-

density devices (Cortex-M3 r1p1-01rel0).

Table 3. Cortex-M3 core limitations and impact on microcontroller behavior

ARM ID

ARM

category

ARM

summary of errata

Impact on high-

density

STM32F10xxx

devices

602117 Cat 2

LDRD with base in list may result in incorrect base register

when interrupted or faulted

Minor

563915 Cat 2 Event register is not set by interrupts and debug Minor

531064 impl SWJ-DP missing POR reset sync No

511864 Cat 3

Cortex-M3 may fetch instructions using incorrect privilege

on return from an exception

532314 Cat 3 DWT CPI counter increments during sleep No

538714 Cat 3 Cortex-M3 TPIU clock domain crossing No

548721 Cat 3 Internal write buffer could be active whilst asleep No

463763 Cat 3 BKPT in debug monitor mode can cause DFSR mismatch Minor

463764 Cat 3 Core may freeze for SLEEPONEXIT single instruction ISR Minor

463769 Cat 3

Unaligned MPU fault during a write may cause the wrong

data to be written to a successful first access

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