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e500mc Core Reference Manual, Rev. 3
xviii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
Figures
1-1 e500mc Block Diagram .......................................................................................................... 1-3
1-2 Example Partitioning Scenario of a Multicore Integrated Device .......................................... 1-4
1-3 GPR Issue Queue (GIQ) ......................................................................................................... 1-9
1-4 Three-Stage Load/Store Unit ................................................................................................ 1-11
2-1 Machine State Register (MSR) ............................................................................................. 2-12
2-2 Processor Version Register (PVR) ........................................................................................ 2-13
2-3 System Version Register (SVR)............................................................................................ 2-13
2-4 Relationship of Timer Facilities to the Time Base................................................................ 2-14
2-5 (Guest) Interrupt Vector Offset Registers ((G)IVORs) ......................................................... 2-18
2-6 (Guest) Exception Syndrome Register (ESR/GESR) ........................................................... 2-20
2-7 Machine Check Syndrome Register (MCSR)....................................................................... 2-23
2-8 Branch Unit Control and Status Register (BUCSR) ............................................................. 2-27
2-9 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-27
2-10 Core Device Control and Status Register 0 (CDCSR0) Format ........................................... 2-29
2-11 L1 Cache Control and Status Register 0 (L1CSR0) Fields Implemented on e500mc .......... 2-30
2-12 L1 Cache Control and Status Register 1 (L1CSR1) Fields Implemented on the e500mc .... 2-32
2-13 L1 Cache Control and Status Register 2 (L1CSR2) Fields Implemented on the e500mc .... 2-34
2-14 L1 Cache Configuration Register 0 (L1CFG0) Fields Implemented on the e500mc ........... 2-35
2-15 L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 2-35
2-16 L2 Cache Configuration Register 0 (L2CFG0)..................................................................... 2-36
2-17 L2 Cache Control and Status Register (L2CSR0)................................................................. 2-37
2-18 L2 Cache Control and Status Register 1 (L2CSR1).............................................................. 2-41
2-19 L2 Cache Error Disable Register (L2ERRDIS) .................................................................... 2-42
2-20 L2 Cache Error Detect Register (L2ERRDET) .................................................................... 2-44
2-21 L2 Cache Error Interrupt Enable Register (L2ERRINTEN)................................................. 2-45
2-22 L2 Cache Error Control Register (L2ERRCTL)................................................................... 2-46
2-23 L2 Cache Error Attribute Register (L2ERRATTR) .............................................................. 2-47
2-24 L2 Cache Error Injection Control Register (L2ERRINJCTL).............................................. 2-48
2-25 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-50
2-26 MMU Configuration Register (MMUCFG).......................................................................... 2-51
2-27 TLB Configuration Registers 0 and 1 (TLB0CFG, TLB1CFG)........................................... 2-52
2-28 MAS Register 0 (MAS0) ...................................................................................................... 2-53
2-29 MAS Register 1 (MAS1) ...................................................................................................... 2-54
2-30 MAS Register 2 (MAS2) ...................................................................................................... 2-55
2-31 MAS Register 3 (MAS3) ...................................................................................................... 2-56
2-32 MAS Register 4 (MAS4) ...................................................................................................... 2-57
2-33 MAS Register 5 (MAS5) ...................................................................................................... 2-58
2-34 MAS Register 6 (MAS6) ...................................................................................................... 2-59
2-35 MAS Register 7 (MAS7) ...................................................................................................... 2-59
2-36 MAS Register 8 (MAS8) Format.......................................................................................... 2-60
2-37 External PID Load Context (EPLC) Format......................................................................... 2-61