威廉·斯托林斯《计算机组织与结构》第七版习题解析

性能设计

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"计算机组织与结构：性能设计（第七版影印版）的习题解答" 本书是《计算机组织与结构：性能设计》第七版的配套习题解答手册，由威廉·斯托林斯（William Stallings）编写。作者保留所有版权，并强调未经许可，不得复制或在互联网上发布相关内容。书中包含所有章节的复习问题和家庭作业问题的答案，旨在帮助读者深入理解计算机组织和结构中的关键概念，以及如何设计高性能的计算机系统。手册内容涵盖了广泛的计算机系统基础知识，包括： 1. **第二章：计算机进化与性能** - 这一章讨论了计算机技术的发展历程，以及如何通过不同的设计选择和技术创新来提升系统的性能指标，如时钟速度、并行处理和能耗效率等。 2. **第三章：计算机功能与互连** - 介绍了计算机内部组件之间的通信方式，包括总线结构、多处理器系统和I/O接口的设计，这些都是理解计算机系统整体性能的关键。 3. **第四章：高速缓存内存** - 高速缓存是提高系统性能的重要组成部分，本章详述了高速缓存的工作原理、替换策略和性能影响因素，如命中率和带宽优化。 4. **第五章：内部内存** - 深入探讨了RAM（随机访问存储器）的类型、工作原理以及如何选择合适的内存技术以优化系统性能。 5. **第六章：外部内存** - 讨论了硬盘、固态驱动器等长期存储设备的特性和与主内存的交互，还包括存储层次结构的设计和优化。 6. **第七章：输入/输出** - I/O系统是连接计算机硬件和用户之间的桥梁，本章讲解了中断、DMA（直接内存访问）和I/O通道等机制，以及它们如何影响系统的响应时间。 7. **第八章：操作系统支持** - 描述了操作系统在管理硬件资源、调度任务、处理并发和提供服务方面的作用，对系统性能的影响和优化方法。 8. **第九章：计算机算术** - 阐述了二进制运算、浮点表示和算术运算单元的设计，这对于理解和解决数值计算中的精度和速度问题至关重要。 9. **第十章：指令集：特征与功能** - 探讨了不同类型的指令集架构，如CISC和RISC，以及它们如何影响处理器性能和软件开发。这本书的习题解答提供了对这些问题的详细分析和解答，有助于学习者检验和巩固他们在理论学习中的理解和应用能力。如果有任何错误或问题，读者可以通过电子邮件向作者报告，以便进行修正和更新。同时，读者可以在作者的网站上查找可能存在的错误表，以获取最新的更正信息。

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and that are combined with the mandatory address/data lines to form a 64-bit

address/data bus. JTAG/Boundary Scan Pins: These signal lines support testing

procedures defined in IEEE Standard 1149.1.

NSWERS TO

ROBLEMS

3.1 Memory (contents in hex): 300: 3005; 301: 5940; 302: 7006

Step 1: 3005 → IR; Step 2: 3 → AC

Step 3: 5940 → IR; Step 4: 3 + 2 = 5 → AC

Step 5: 7006 → IR; Step 6: AC → Device 6

3.2 1. a. The PC contains 300, the address of the first instruction. This value is loaded

in to the MAR.

b. The value in location 300 (which is the instruction with the value 1940 in

hexadecimal) is loaded into the MBR, and the PC is incremented. These two

steps can be done in parallel.

c. The value in the MBR is loaded into the IR.

2. a. The address portion of the IR (940) is loaded into the MAR.

b. The value in location 940 is loaded into the MBR.

c. The value in the MBR is loaded into the AC.

3. a. The value in the PC (301) is loaded in to the MAR.

b. The value in location 301 (which is the instruction with the value 5941) is

loaded into the MBR, and the PC is incremented.

c. The value in the MBR is loaded into the IR.

4. a. The address portion of the IR (941) is loaded into the MAR.

b. The value in location 941 is loaded into the MBR.

c. The old value of the AC and the value of location MBR are added and the

result is stored in the AC.

5. a. The value in the PC (302) is loaded in to the MAR.

b. The value in location 302 (which is the instruction with the value 2941) is

loaded into the MBR, and the PC is incremented.

c. The value in the MBR is loaded into the IR.

6. a. The address portion of the IR (941) is loaded into the MAR.

b. The value in the AC is loaded into the MBR.

c. The value in the MBR is stored in location 941.

3.3 a. 2

= 16 MBytes

b. (1) If the local address bus is 32 bits, the whole address can be transferred at

once and decoded in memory. However, because the data bus is only 16 bits, it

will require 2 cycles to fetch a 32-bit instruction or operand.

(2) The 16 bits of the address placed on the address bus can't access the whole

memory. Thus a more complex memory interface control is needed to latch the

first part of the address and then the second part (because the microprocessor

will end in two steps). For a 32-bit address, one may assume the first half will

decode to access a "row" in memory, while the second half is sent later to access

a "column" in memory. In addition to the two-step address operation, the

microprocessor will need 2 cycles to fetch the 32 bit instruction/operand.

c. The program counter must be at least 24 bits. Typically, a 32-bit microprocessor

will have a 32-bit external address bus and a 32-bit program counter, unless on-

chip segment registers are used that may work with a smaller program counter.

If the instruction register is to contain the whole instruction, it will have to be

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32-bits long; if it will contain only the op code (called the op code register) then

it will have to be 8 bits long.

3.4 In cases (a) and (b), the microprocessor will be able to access 2

= 64K bytes; the

only difference is that with an 8-bit memory each access will transfer a byte, while

with a 16-bit memory an access may transfer a byte or a 16-byte word. For case (c),

separate input and output instructions are needed, whose execution will generate

separate "I/O signals" (different from the "memory signals" generated with the

execution of memory-type instructions); at a minimum, one additional output pin

will be required to carry this new signal. For case (d), it can support 2

= 256 input

and 2

= 256 output byte ports and the same number of input and output 16-bit

ports; in either case, the distinction between an input and an output port is defined

by the different signal that the executed input or output instruction generated.

3.5 Clock cycle =

8 MHz

= 125 ns

Bus cycle = 4 × 125 ns = 500 ns

2 bytes transferred every 500 ns; thus transfer rate = 4 MBytes/sec

Doubling the frequency may mean adopting a new chip manufacturing technology

(assuming each instructions will have the same number of clock cycles); doubling

the external data bus means wider (maybe newer) on-chip data bus drivers/latches

and modifications to the bus control logic. In the first case, the speed of the memory

chips will also need to double (roughly) not to slow down the microprocessor; in

the second case, the "wordlength" of the memory will have to double to be able to

send/receive 32-bit quantities.

3.6 a. Input from the Teletype is stored in INPR. The INPR will only accept data from

the Teletype when FGI=0. When data arrives, it is stored in INPR, and FGI is

set to 1. The CPU periodically checks FGI. If FGI =1, the CPU transfers the

contents of INPR to the AC and sets FGI to 0.

When the CPU has data to send to the Teletype, it checks FGO. If FGO = 0,

the CPU must wait. If FGO = 1, the CPU transfers the contents of the AC to

OUTR and sets FGO to 0. The Teletype sets FGI to 1 after the word is printed.

b. The process described in (a) is very wasteful. The CPU, which is much faster

than the Teletype, must repeatedly check FGI and FGO. If interrupts are used,

the Teletype can issue an interrupt to the CPU whenever it is ready to accept or

send data. The IEN register can be set by the CPU (under programmer control)

3.7 a. During a single bus cycle, the 8-bit microprocessor transfers one byte while the

16-bit microprocessor transfers two bytes. The 16-bit microprocessor has twice

the data transfer rate.

b. Suppose we do 100 transfers of operands and instructions, of which 50 are one

byte long and 50 are two bytes long. The 8-bit microprocessor takes 50 + (2 x

50) = 150 bus cycles for the transfer. The 16-bit microprocessor requires 50 + 50

= 100 bus cycles. Thus, the data transfer rates differ by a factor of 1.5. Source:

[PROT88].

3.8 The whole point of the clock is to define event times on the bus; therefore, we wish

for a bus arbitration operation to be made each clock cycle. This requires that the

priority signal propagate the length of the daisy chain (Figure 3.26) in one clock

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period. Thus, the maximum number of masters is determined by dividing the

amount of time it takes a bus master to pass through the bus priority by the clock

period.

3.9 The lowest-priority device is assigned priority 16. This device must defer to all the

others. However, it may transmit in any slot not reserved by the other SBI devices.

3.10 At the beginning of any slot, if none of the TR lines is asserted, only the priority 16

device may transmit. This gives it the lowest average wait time under most

circumstances. Only when there is heavy demand on the bus, which means that

most of the time there is at least one pending request, will the priority 16 device

not have the lowest average wait time.

3.11 a. With a clocking frequency of 10 MHz, the clock period is 10

–9

s = 100 ns. The

length of the memory read cycle is 300 ns.

b. The Read signal begins to fall at 75 ns from the beginning of the third clock

cycle (middle of the second half of T

). Thus, memory must place the data on

the bus no later than 55 ns from the beginning of T

. Source: [PROT88]

3.12 a. The clock period is 125 ns. Therefore, two clock cycles need to be inserted.

b. From Figure 3.19, the Read signal begins to rise early in T

. To insert two clock

cycles, the Ready line can be put in low at the beginning of T

and kept low for

250 ns. Source: [PROT88]

3.13 a. A 5 MHz clock corresponds to a clock period of 200 ns. Therefore, the Write

signal has a duration of 150 ns.

b. The data remain valid for 150 + 20 = 170 ns.

c. One wait state. Source: [PROT88]

3.14 a. Without the wait states, the instruction takes 16 bus clock cycles. The

instruction requires four memory accesses, resulting in 8 wait states. The

instruction, with wait states, takes 24 clock cycles, for an increase of 50%.

b. In this case, the instruction takes 26 bus cycles without wait states and 34 bus

cycles with wait states, for an increase of 33%. Source: [PROT88]

3.15 a. The clock period is 125 ns. One bus read cycle takes 500 ns = 0.5 µs. If the bus

cycles repeat one after another, we can achieve a data transfer rate of 2 MB/s.

b. The wait state extends the bus read cycle by 125 ns, for a total duration of 0.625

µs. The corresponding data transfer rate is 1/0.625 = 1.6 MB/s. Source:

[PROT88]

3.16 A bus cycle takes 0.25 µs, so a memory cycle takes 1 µs. If both operands are even-

aligned, it takes 2 µs to fetch the two operands. If one is odd-aligned, the time

required is 3 µs. If both are odd-aligned, the time required is 4 µs. Source:

[PROT88].

3.17 Consider a mix of 100 instructions and operands. On average, they consist of 20 32-

bit items, 40 16-bit items, and 40 bytes. The number of bus cycles required for the

16-bit microprocessor is (2 × 20) + 40 + 40 = 120. For the 32-bit microprocessor, the

number required is 100. This amounts to an improvement of 20/120 or about 17%.

Source: [PROT88].

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