ADuCM320i/322/322I ARM Cortex-M3 MCU用户指南：功能与特性详解

需积分: 9 51 浏览量更新于2024-07-17 收藏 2.34MB PDF 举报

本文档是关于AduCM320i、ADuCM322和ADuCM322i系列嵌入式微控制器的用户指南（UG-868），由Analog Devices公司发布。该系列微控制器基于ARM Cortex-M3内核，提供了丰富的功能和特性。以下是文档的主要知识点： 1. **功能与特性描述**：手册详细介绍了ADuCM320i/ADuCM322/ADuCM322i的功能性和硬件架构，包括其内存配置（2个128kB Flash和32kB SRAM）、ARM Cortex-M3处理器、多路复用器（MUX）、用于模拟输入的A/D转换通道（AIN0到AIN15）、电压参考缓冲器（BUF_VREF2V5）以及数字-模拟转换器（VDACs和IDACs）。 2. **硬件组件**： - **电源管理**：包括PVDDx, AGNDx, IOVDDx, IOGNDx等电源引脚。 - **通用I/O端口**：包括GPIO端口、SWDIO和SWCLK用于调试接口，以及多个串行接口（UART、2个SPI和2个I2C）。 - **扩展中断（EXTIRQs）**：支持外部中断事件处理。 - **MDIO**：管理媒体访问控制（MAC）接口。 - **片上逻辑加速器（PLA）**：可能包含内置的算法加速或专用逻辑。 - **内部传感器和定时器**：包括温度传感器、Watchdog Timer、Wake-up Timer、PWM生成器、VDACs和高级模拟-数字转换器（14位SAR ADC）。 - **系统管理**：如Serial Wire Debug (SWD)系统时钟、80MHz PLL和低速晶体振荡器（32.768kHz）。 3. **警告与许可**：文档末尾包含了重要的警告和条款及条件，确保在使用前阅读，了解潜在的风险和法律责任。 4. **图示**：文档中包含详细的ADuCM320i的Functional Block Diagram（如Figure 1），直观展示了各个模块的连接和功能布局。通过阅读这份用户指南，开发人员可以深入了解如何利用ADuCM320i/ADuCM322/ADuCM322i的特性进行嵌入式系统设计，包括编程接口、外围设备配置和电源管理，从而优化他们的项目性能和稳定性。

UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual

Rev. B | Page 16 of 192

Table 8. Power Management Register Summary

Address Name Description Reset Access

0x40002400

PWRMOD

Power modes

0x0000

0x40002404 PWRKEY Key protection for PWRMOD 0x0000 RW

Power Modes Register

Address: 0x40002400, Reset: 0x0000, Name: PWRMOD

Table 9. Bit Descriptions for PWRMOD

Bit(s) Bit Name Description Reset Access

[14:2] RESERVED Reserved. These bits must write 0 by user code. 0x0 R

[1:0] PWRMOD Power modes control bits. When read, these bits contain the last power mode value entered

by user code. Note that, to place the Cortex in sleep deep mode for hibernate, the Cortex-M3

system control register (Address 0xE000ED10) must be configured to 0x4 or 0x06.

0x0 RW

00: active mode

01: CORE_SLEEP mode

10: SYS_SLEEP mode

11: hibernate mode

Key Protection for PWRMOD Register

Address: 0x40002404, Reset: 0x0000, Name: PWRKEY

Table 10. Bit Descriptions for PWRKEY

Bit(s) Bit Name Description Reset Access

[15:0] PWRKEY Power control key register. The PWRMOD register is key protected. Two writes to the key are

necessary to change the value in the PWRMOD register: first 0x4859, then 0xF27B. Then, write

to the PWRMOD register. A write to any other register before writing to PWRMOD returns the

protection to the lock state.

0x0 RW

ADuCM320i/ADuCM322/ADuCM322i Reference Manual UG-868

Rev. B | Page 17 of 192

ARM CORTEX-M3 PROCESSOR

ARM CORTEX-M3 PROCESSOR FEATURES

High Performance

• 1.25 DMIPS/MHz.

• Many instructions, including multiply, are single cycle.

• Separate data and instruction buses allow simultaneous data and instruction accesses to be performed.

• Optimized for single cycle flash usage.

Low Power

• Low standby current.

• Core implemented using advanced clock gating so that only the actively used logic consumes dynamic power.

• Power saving mode support (sleep and deep sleep modes). The design has separate clocks to allow unused parts of the processor to

be stopped.

Advanced Interrupt Handling

• The nested vectored interrupt controller (NVIC) supports up to 240 interrupts. The ADuCM320i/ADuCM322/ADuCM322i supports

47 of these interrupts. The vectored interrupt feature greatly reduces interrupt latency because there is no need for software to determine

which interrupt handler to serve. In addition, there is no need to have software to set up nested interrupt support.

• The ARM Cortex-M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves them at the exit

interrupt. The pushing and retrieving helps reduce interrupt handling latency and allow interrupt handlers to be normal C functions.

• Dynamic priority control for each interrupt.

• Latency reduction using late arrival interrupt acceptance and tail-chain interrupt entry.

• Immediate execution of a nonmaskable interrupt request for safety critical applications.

System Features

• Support for bit band operation and unaligned data access.

• Advanced fault handling features include various exception types and fault status registers.

Debug Support

• Serial wire debug interfaces (SW-DP).

• Flash patch and breakpoint (FPB) unit for implementing breakpoints. Limited to two hardware breakpoints.

• Data watchpoint and trigger (DWT) unit for implementing watchpoints trigger resources and system profiling. Limited to one

hardware watchpoint. The DWT does not support data matching for watchpoint generation because it only has one comparator.

ARM CORTEX-M3 PROCESSOR OVERVIEW

The ADuCM320i/ADuCM322/ADuCM322i contain an embedded ARM Cortex-M3 processor, Revision r2p1. The ARM Cortex-M3

processor provides a high performance, low cost platform that meets the system requirements of minimal memory implementation,

reduced pin count, and low power consumption while delivering outstanding computational performance and exceptional system

response to interrupts.

ARM CORTEX-M3 PROCESSOR OPERATION

Several ARM Cortex-M3 processor components are flexible in their implementation. This section details the actual implementation of

these components in the ADuCM320i/ADuCM322/ADuCM322i.

Serial Wire Debug (SW/JTAG-DP)

The ADuCM320i/ADuCM322/ADuCM322i only support the serial wire interface via the SWCLK and SWDIO pins. It does not support

the 5-wire JTAG interface.

ROM Table

The ADuCM320i/ADuCM322/ADuCM322i implement the default ROM table.

UG-868 ADuCM320i/ADuCM322/ADuCM322i Reference Manual

Rev. B | Page 20 of 192

ADC CIRCUIT OVERVIEW

The ADuCM320i/ADuCM322/ADuCM322i incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit (ADuCM320i)

or 12-bit (ADuCM322/ADuCM322i) accurate. It can operate from a 2.9 V to 3.6 V supply and is capable of providing a throughput of up

to 1 MSPS. This ADC block provides the user with a multichannel multiplexer, input buffer for high impedance input channels (ADuCM320i

only), on-chip reference, and SAR ADC.

The SAR ADC circuit is implemented on the low voltage analog die. The ARM Cortex-M3 processor interfaces to the ADC via an

internal parallel die to die interface.

Depending on the input signal configuration, the ADC can operate in one of the following two modes:

 Differential mode measures the difference between two signals.

 Single-ended mode measures any signal relative to AGND.

The converter accepts an analog input range of 0 to V

REF

when operating in single-ended mode. In fully differential mode, the input signal

must be balanced around a common-mode voltage (V

) in the 0 V to AV

range and with a maximum amplitude of 2 × V

REF

FS (V

REF

)

–FS (–V

REF

)

IN+

AIN–

OUTPUT CODE

13437-105

Figure 6. Examples of Balanced Signals for Differential Mode

A high precision, low drift, factory-calibrated 2.51 V reference is provided on-chip. An external reference can also be connected to the

ADC_REFP and ADC_REFN pins.

Single or continuous conversion modes can be initiated in the software. An external pin (alternate function of P2.4) can also generate a

repetitive trigger for ADC conversions.

ADC CIRCUIT OPERATION

The SAR ADC is based on a charge redistribution DAC. The capacitive DAC consists of two identical arrays of 18 binary weighted

capacitors that are connected to the two inputs of the comparator.

The ADC converts the voltage applied to AIN+ and AIN− in the following three phases:

1. During the precharge phase, the precharge buffers connect the inputs to the capacitor arrays, which charges the capacitors quickly

with minimal loading of the external input source.

2. During the acquisition phase, the capacitor arrays are connected directly to the inputs to fully charge the capacitor arrays and

eliminate any precharge buffer errors. The timing for the acquisition phase is set by ADCCNVC[25:16]. This value must be set to 500 ns. If

the input buffer is not used when measuring AV

/2, IOV

/2, or temperature sensor channels, set this value to 1.5 μs.

3. At the end of the acquisition phase, the internal CNV signal goes high and initiates the conversion phase. The conversion begins with

the SW+ and SW− switches opening, which disconnects the two capacitor arrays from the analog inputs and connects the analog

inputs to the AGND (−V

REF

) input. The conversion is completed by normal successive approximation.

The ADC block operates from an internally generated 20 MHz clock.

The ADC conversion rate is set by ADCCNVC[9:0].

剩余191页未读，继续阅读

long_ly

粉丝: 3
资源: 9

ADuCM320i/322/322I ARM Cortex-M3 MCU用户指南：功能与特性详解

多米诺（Domino）喷码机使用指南

ADuCM320 参考手册

基于单片机ADuCM320i的光电收发模块控制设计.pdf

ADuCM320i学习

30,300,31,310,32,320i_ENG.pdf

BMW宝马320i-328i-335i汽车使用手册用户说明书pdf电子版下载.pdf

KYL-320I使用说明书

FPGA可编程逻辑器件芯片XC3S100E-4FGG320I中文规格书.pdf

FPGA可编程逻辑器件芯片XC3S100E-4FGG320I中文规格书.docx

FPGA可编程逻辑器件芯片XC3S100E-5FG320I中文规格书.pdf

最新资源