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首页全志H5四核OTT盒处理器技术规格详细手册
"全志H5芯片数据手册,包含详尽的芯片信息,超过700页,涵盖了所有参数,是开发和设计基于全志H5芯片产品的关键参考资料。"
全志H5是一款四核OTT(Over-The-Top)盒子处理器,由全志科技公司制造。该芯片的手册详细介绍了其设计规格、功能特性和使用注意事项,为开发者和工程师提供了丰富的技术信息。手册的修订版本为1.0,发布日期为2016年5月20日。
全志H5芯片的主要特点可能包括高性能的四核处理能力,适合处理复杂的多媒体任务,如高清视频解码和流畅的用户界面。在OTT应用中,这样的处理器通常用于智能电视盒、媒体播放器和其他连接设备,提供互联网内容的访问和流媒体服务。
手册中的内容可能涵盖了以下部分:
1. **芯片架构**:包括CPU核心的详细信息,如使用的ARM Cortex-A53架构,以及可能集成的GPU和其他辅助处理器。
2. **内存接口**:描述了H5芯片与DDR内存的交互方式,包括支持的内存类型、速度和容量。
3. **多媒体支持**:可能包括高清视频解码和编码的能力,如H.265 (HEVC) 和 H.264 (AVC),以及对音频编解码器的支持。
4. **I/O接口**:详述了芯片提供的各种接口,如USB、Ethernet、HDMI、SPI、I2C和GPIO等,用于与其他硬件组件通信。
5. **电源管理**:说明了芯片的功耗特性,以及如何实现低功耗模式以优化能效。
6. **开发工具和SDK**:可能提供软件开发工具和SDK(Software Development Kit)的概述,帮助开发者构建应用程序和驱动程序。
7. **安全特性**:可能包括加密引擎、数字版权管理(DRM)支持以及安全启动等特性,以确保内容保护和系统安全。
8. **热设计和物理规格**:给出了芯片的封装尺寸、散热需求以及推荐的布局指导。
全志科技在手册中声明,所有信息均视为准确可靠,但保留随时更改电路设计和规格的权利,且不承担因使用其产品导致的任何专利侵权或其他第三方权利的法律责任。此外,手册明确表示,未获得书面许可,不得复制或部分复制内容,且使用芯片可能需要获取第三方的许可。
全志H5芯片数据手册是开发基于全志H5芯片的OTT设备时不可或缺的技术文档,包含了从硬件设计到软件开发所需的所有基本信息。
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 16
4.22.3.8. PL PULL Register 0 (Default Value: 0x0000_0005) ..................................................................... 328
4.22.3.9. PL PULL Register 1 (Default Value: 0x0000_0000) ..................................................................... 328
4.22.3.10. PL External Interrupt Configure Register 0 (Default Value: 0x0000_0000) .............................. 328
4.22.3.11. PL External Interrupt Configure Register 1 (Default Value: 0x0000_0000) .............................. 328
4.22.3.12. PL External Interrupt Configure Register 2 (Default Value: 0x0000_0000) .............................. 329
4.22.3.13. PL External Interrupt Configure Register 3 (Default Value: 0x0000_0000) .............................. 329
4.22.3.14. PL External Interrupt Control Register (Default Value: 0x0000_0000) ..................................... 329
4.22.3.15. PL External Interrupt Status Register (Default Value: 0x0000_0000) ....................................... 329
4.22.3.16. PL External Interrupt Debounce Register (Default Value: 0x0000_0000) ................................ 330
Chapter 5 Memory ......................................................................................................................................................... 331
5.1. SDRAM Controller(DRAMC) ............................................................................................................................... 332
5.1.1. Overview ................................................................................................................................................. 332
5.2. NAND Flash Controller(NDFC) ............................................................................................................................ 333
5.2.1. Overview ................................................................................................................................................. 333
5.2.2. Block Diagram ......................................................................................................................................... 333
5.2.3. Operations and Functional Descriptions ................................................................................................. 334
5.2.3.1. External Signals ............................................................................................................................ 334
5.2.3.2. Clock Sources................................................................................................................................ 335
5.2.3.3. NDFC Timing Diagram .................................................................................................................. 335
5.2.3.4. NDFC Operation Guide ................................................................................................................. 341
5.2.4. Register List ............................................................................................................................................. 343
5.2.5. Register Description ................................................................................................................................ 344
5.2.5.1. NDFC Control Register (Default Value: 0x0000_0000) ................................................................. 344
5.2.5.2. NDFC Status Register (Default Value: 0x0000_0F00) ................................................................... 346
5.2.5.3. NDFC Interrupt and DMA Enable Register (Default Value: 0x0000_0000) ................................... 347
5.2.5.4. NDFC Timing Control Register (Default Value: 0x0000_0000) ..................................................... 348
5.2.5.5. NDFC Timing Configure Register (Default Value: 0x0000_0095) ................................................. 348
5.2.5.6. NDFC Address Low Word Register (Default Value: 0x0000_0000) ............................................... 350
5.2.5.7. NDFC Address High Word Register (Default Value: 0x0000_0000) .............................................. 350
5.2.5.8. NDFC Data Block Number Register (Default Value: 0x0000_0000) .............................................. 351
5.2.5.9. NDFC Data Counter Register (Default Value: 0x0000_0000) ........................................................ 351
5.2.5.10. NDFC Command IO Register (Default Value: 0x0000_0000) ...................................................... 351
5.2.5.11. NDFC Command Set Register 0 (Default Value: 0x00E0_0530).................................................. 353
5.2.5.12. NDFC Command Set Register 1 (Default Value: 0x7000_8510).................................................. 354
5.2.5.13. NDFC ECC Control Register (Default Value: 0x4A80_0008) ........................................................ 354
5.2.5.14. NDFC ECC Status Register (Default Value: 0x0000_0000) .......................................................... 355
5.2.5.15. NDFC Enhanced Feature Register (Default Value: 0x0000_0000) .............................................. 356
5.2.5.16. NDFC Error Counter Register 0 (Default Value: 0x0000_0000) .................................................. 356
5.2.5.17. NDFC Error Counter Register 1 (Default Value: 0x0000_0000) .................................................. 357
5.2.5.18. NDFC Error Counter Register 2 (Default Value: 0x0000_0000) .................................................. 359
5.2.5.19. NDFC Error Counter Register 3 (Default Value: 0x0000_0000) .................................................. 360
5.2.5.20. NDFC User Data Register [N] (Default Value: 0xFFFF_FFFF) ....................................................... 361
5.2.5.21. NDFC EFNAND STATUS Register (Default Value: 0x0000_0000) ................................................. 361
5.2.5.22. NDFC Spare Area Register (Default Value: 0x0000_0400) .......................................................... 361
5.2.5.23. NDFC Pattern ID Register (Default Value: 0x0000_0000) ........................................................... 361
5.2.5.24. NDFC Read Data Status Control Register (Default Value: 0x0100_0000) ................................... 364
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 17
5.2.5.25. NDFC Read Data Status Register 0 (Default Value: 0x0000_0000) ............................................. 364
5.2.5.26. NDFC Read Data Status Register 1 (Default Value: 0x0000_0000) ............................................. 364
5.2.5.27. NDFC MBUS DMA Address Register (Default Value: 0x0000_0000) .......................................... 365
5.2.5.28. NDFC MBUS DMA Byte Counter Register (Default Value: 0x0000_0000) .................................. 365
5.2.5.29. NDFC Normal DMA Mode Control Register (Default Value: 0x0000_00A5) .............................. 365
5.2.5.30. NDFC IO Data Register (Default Value: 0x0000_0000) ............................................................... 365
5.3. SD/MMC Host Controller(SMHC) ....................................................................................................................... 366
5.3.1. Overview ................................................................................................................................................. 366
5.3.2. Block Diagram ......................................................................................................................................... 366
5.3.3. Operations and Functional Descriptions ................................................................................................. 367
5.3.3.1. External Signals ............................................................................................................................ 367
5.3.3.2. Clock Sources................................................................................................................................ 367
5.3.3.3. SMHC Timing Diagram ................................................................................................................. 367
5.3.3.4. Internal DMA Controller Description ........................................................................................... 368
5.3.3.5. Calibrate Delay Chain ................................................................................................................... 370
5.3.4. Register List ............................................................................................................................................. 370
5.3.5. Register Description ................................................................................................................................ 372
5.3.5.1. SMHC Global Control Register (Default Value: 0x0000_0100) ..................................................... 372
5.3.5.2. SMHC Clock Control Register (Default Value: 0x0000_0000) ....................................................... 373
5.3.5.3. SMHC Timeout Register (Default Value: 0xFFFF_FF40)................................................................ 374
5.3.5.4. SMHC Bus Width Register (Default Value: 0x0000_0000) ........................................................... 374
5.3.5.5. SMHC Block Size Register (Default Value: 0x0000_0200) ............................................................ 374
5.3.5.6. SMHC Block Count Register (Default Value: 0x0000_0200) ......................................................... 374
5.3.5.7. SMHC Command Register (Default Value: 0x0000_0000)............................................................ 375
5.3.5.8. SMHC Command Argument Register (Default Value: 0x0000_0000) .......................................... 377
5.3.5.9. SMHC Response 0 Register (Default Value: 0x0000_0000) .......................................................... 377
5.3.5.10. SMHC Response 1 Register (Default Value: 0x0000_0000) ........................................................ 377
5.3.5.11. SMHC Response 2 Register (Default Value: 0x0000_0000) ........................................................ 377
5.3.5.12. SMHC Response 3 Register (Default Value: 0x0000_0000) ........................................................ 378
5.3.5.13. SMHC Interrupt Mask Register (Default Value: 0x0000_0000) .................................................. 378
5.3.5.14. SMHC Masked Interrupt Status Register (Default Value: 0x0000_0000) ................................... 379
5.3.5.15. SMHC Raw Interrupt Status Register (Default Value: 0x0000_0000) ......................................... 380
5.3.5.16. SMHC Status Register (Default Value: 0x0000_0006) ................................................................ 382
5.3.5.17. SMHC FIFO Water Level Register (Default Value: 0x000F_0000) ............................................... 383
5.3.5.18. SMHC Function Select Register (Default Value: 0x0000_0000) ................................................. 384
5.3.5.19. SMHC Transferred Byte Count Register0 (Default Value: 0x0000_0000) ................................... 385
5.3.5.20. SMHC Transferred Byte Count Register1 (Default Value: 0x0000_0000) ................................... 385
5.3.5.21. SMHC Auto Command 12 Argument Register (Default Value: 0x0000_FFFF) ............................ 386
5.3.5.22. SMHC New Timing Set Register (Default Value: 0x8171_0000) ................................................. 386
5.3.5.23. SMHC Hardware Reset Register (Default Value: 0x0000_0001) ................................................. 387
5.3.5.24. SMHC DMAC Control Register (Default Value: 0x0000_0000) ................................................... 387
5.3.5.25. SMHC Descriptor List Base Address Register (Default Value: 0x0000_0000) ............................. 388
5.3.5.26. SMHC DMAC Status Register (Default Value: 0x0000_0000) ..................................................... 389
5.3.5.27. SMHC DMAC Interrupt Enable Register (Default Value: 0x0000_0000) ..................................... 390
5.3.5.28. SMHC Current Host Descriptor Address Register (Default Value: 0x0000_0000) ...................... 391
5.3.5.29. SMHC Current Buffer Descriptor Address Register (Default Value: 0x0000_0000) .................... 391
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 18
5.3.5.30. SMHC Card Threshold Control Register (Default Value: 0x0000_0000) ..................................... 392
5.3.5.31. SMHC eMMC4.5 DDR Start Bit Detection Control Register (Default Value: 0x0000_0000) ....... 392
5.3.5.32. SMHC Response CRC Register (Default Value: 0x0000_0000) ................................................... 393
5.3.5.33. SMHC Data7 CRC Register (Default Value: 0x0000_0000) ......................................................... 393
5.3.5.34. SMHC Data6 CRC Register (Default Value: 0x0000_0000) ......................................................... 394
5.3.5.35. SMHC Data5 CRC Register (Default Value: 0x0000_0000) ......................................................... 394
5.3.5.36. SMHC Data4 CRC Register (Default Value: 0x0000_0000) ......................................................... 394
5.3.5.37. SMHC Data3 CRC Register (Default Value: 0x0000_0000) ......................................................... 395
5.3.5.38. SMHC Data2 CRC Register (Default Value: 0x0000_0000) ......................................................... 395
5.3.5.39. SMHC Data1 CRC Register (Default Value: 0x0000_0000) ......................................................... 395
5.3.5.40. SMHC Data0 CRC Register (Default Value: 0x0000_0000) ......................................................... 396
5.3.5.41. SMHC CRC Status Register (Default Value: 0x0000_0000) ......................................................... 396
5.3.5.42. SMHC Drive Delay Control Register (Default Value: 0x0001_0000) ........................................... 396
5.3.5.43. SMHC Sample Delay Control Register (Default Value: 0x0000_2000) ........................................ 397
5.3.5.44. SMHC Data Strobe Delay Control Register (Default Value: 0x0000_2000) ................................ 397
5.3.5.45. SMHC FIFO Register (Default Value: 0x0000_0000) ................................................................... 398
Chapter 6 Image ............................................................................................................................................................. 399
6.1. CSI....................................................................................................................................................................... 400
6.1.1. Overview ................................................................................................................................................. 400
6.1.2. Block Diagram ......................................................................................................................................... 401
6.1.3. Operations and Functional Descriptions ................................................................................................. 402
6.1.3.1. CSI FIFO Distribution .................................................................................................................... 402
6.1.3.2. CSI Timing..................................................................................................................................... 402
6.1.3.3. Bit Definition ................................................................................................................................ 403
6.1.4. Register list .............................................................................................................................................. 403
6.1.5. Register Description ................................................................................................................................ 404
6.1.5.1. CSI Enable Register (Default Value: 0x0000_0000) ...................................................................... 404
6.1.5.2. CSI Interface Configuration Register (Default Value: 0x0005_0000) ............................................ 405
6.1.5.3. CSI Capture Register (Default Value: 0x0000_0000) .................................................................... 407
6.1.5.4. CSI Synchronization Counter Register (Default Value: 0x0000_0000) ......................................... 407
6.1.5.5. CSI FIFO Threshold Register (Default Value: 0x040F_0400) ......................................................... 408
6.1.5.6. CSI Pattern Generation Length Register (Default Value: 0x0000_0000) ...................................... 408
6.1.5.7. CSI Pattern Generation Address Register (Default Value: 0x0000_0000) .................................... 408
6.1.5.8. CSI Version Register (Default Value: 0x0000_0000) ..................................................................... 408
6.1.5.9. CSI Channel_0 Configuration Register (Default Value: 0x0030_0200) ......................................... 409
6.1.5.10. CSI Channel_0 Scale Register (Default Value: 0x0000_0000) ..................................................... 411
6.1.5.11. CSI Channel_0 FIFO 0 Output Buffer-A Address Register (Default Value: 0x0000_0000) .......... 411
6.1.5.12. CSI Channel_0 FIFO 1 Output Buffer-A Address Register (Default Value: 0x0000_0000) .......... 411
6.1.5.13. CSI Channel_0 FIFO 2 Output Buffer-A Address Register (Default Value: 0x0000_0000) .......... 412
6.1.5.14. CSI Channel_0 Status Register (Default Value: 0x0000_0000) ................................................... 412
6.1.5.15. CSI Channel_0 Interrupt Enable Register (Default Value: 0x0000_0000)................................... 412
6.1.5.16. CSI Channel_0 Interrupt Status Register (Default Value: 0x0000_0000) ................................... 413
6.1.5.17. CSI Channel_0 Horizontal Size Register (Default Value: 0x0500_0000) ..................................... 414
6.1.5.18. CSI Channel_0 Vertical Size Register (Default Value: 0x01E0_0000) .......................................... 414
6.1.5.19. CSI Channel_0 Buffer Length Register (Default Value: 0x0140_0280) ....................................... 414
6.1.5.20. CSI Channel_0 Flip Size Register (Default Value: 0x01E0_0280) ................................................ 415
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 19
6.1.5.21. CSI Channel_0 Frame Clock Counter Register (Default Value: 0x0000_0000) ........................... 415
6.1.5.22. CSI Channel_0 accumulated and internal clock counter Register (Default Value: 0x0000_0000)
................................................................................................................................................................... 415
6.1.5.23. CSI Channel_0 FIFO Statistic Register (Default Value: 0x0000_0000) ........................................ 415
6.1.5.24. CSI Channel_0 PCLK Statistic Register (Default Value: 0x0000_7FFF) ........................................ 416
6.1.5.25. CCI Control Register (Default Value: 0x0000_0000) ................................................................... 416
6.1.5.26. CCI Transmission Configuration Register (Default Value: 0x1000_0000) ................................... 418
6.1.5.27. CCI Packet Format Register (Default Value: 0x0011_0001) ........................................................ 418
6.1.5.28. CCI Bus Control Register (Default Value: 0x0000_2500) ............................................................ 419
6.1.5.29. CCI Interrupt Control Register (Default Value: 0x0000_0000) ................................................... 420
6.1.5.30. CCI Line Counter Trigger Control Register (Default Value: 0x0000_0000) ................................. 420
6.1.5.31. CCI FIFO Access Register (Default Value: 0x0000_0000) ............................................................ 420
Chapter 7 Display ........................................................................................................................................................... 421
7.1. DE2.0 .................................................................................................................................................................. 422
7.1.1. Overview ................................................................................................................................................. 422
7.2. TCON .................................................................................................................................................................. 423
7.2.1. Overview ................................................................................................................................................. 423
7.2.2. Block Diagram ......................................................................................................................................... 423
7.2.3. Operations and Functional Descriptions ................................................................................................. 423
7.2.3.1. RGB Gamma Correction ............................................................................................................... 423
7.2.3.2. CEU Module ................................................................................................................................. 424
7.2.4. TCON0 Module Register List ................................................................................................................... 424
7.2.5. TCON0 Module Register Description ...................................................................................................... 425
7.2.5.1. TCON Global Control Register (Default Value: 0x0000_0000) ...................................................... 425
7.2.5.2. TCON Global Interrupt Register0 (Default Value: 0x0000_0000) ................................................. 425
7.2.5.3. TCON Global Interrupt Register1 (Default Value: 0x0000_0000) ................................................. 426
7.2.5.4. TCON1 Control Register (Default Value: 0x0000_0000) ............................................................... 426
7.2.5.5. TCON1 Basic Timing Register0 (Default Value: 0x0000_0000) ..................................................... 426
7.2.5.6. TCON1 Basic Timing Register1 (Default Value: 0x0000_0000) ..................................................... 427
7.2.5.7. TCON1 Basic Timing Register2 (Default Value: 0x0000_0000) ..................................................... 427
7.2.5.8. TCON1 Basic Timing Register3 (Default Value: 0x0000_0000) ..................................................... 427
7.2.5.9. TCON1 Basic Timing Register4 (Default Value: 0x0000_0000) ..................................................... 428
7.2.5.10. TCON1 Basic Timing Register5 (Default Value: 0x0000_0000) ................................................... 428
7.2.5.11. TCON1 SYNC Register (Default Value: 0x0000_0000) ................................................................ 428
7.2.5.12. TCON1 IO Polarity Register (Default Value: 0x0000_0000) ........................................................ 428
7.2.5.13. TCON1 IO Trigger Register (Default Value: 0x0FFF_FFFF)........................................................... 429
7.2.5.14. TCON ECC FIFO Register (Default Value: UDF) ............................................................................ 430
7.2.5.15. TCON CEU Control Register (Default Value: 0x0000_0000) ....................................................... 430
7.2.5.16. TCON CEU Coefficient MUL Register (Default Value: 0x0000_0000) ......................................... 430
7.2.5.17. TCON CEU Coefficient Add Register (Default Value: 0x0000_0000) ........................................... 431
7.2.5.18. TCON CEU Coefficient Range Register (Default Value: 0x0000_0000) ....................................... 431
7.2.5.19. TCON Safe Period Register (Default Value: 0x0000_0000) ......................................................... 431
7.2.5.20. TCON1 Fill Control Register (Default Value: 0x0000_0000) ....................................................... 432
7.2.5.21. TCON1 Fill Begin Register (Default Value: 0x0000_0000) .......................................................... 432
7.2.5.22. TCON1 Fill End Register (Default Value: 0x0000_0000) ............................................................. 432
7.2.5.23. TCON1 Fill Data Register (Default Value: 0x0000_0000) ............................................................ 432
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 20
7.2.6. TCON1 Module Register List ................................................................................................................... 433
7.2.7. TCON1 Module Register Description ...................................................................................................... 433
7.2.7.1. TCON Global Control Register (Default Value: 0x0000_0000) ...................................................... 433
7.2.7.2. TCON Global Interrupt Register0 (Default Value: 0x0000_0000) ................................................. 434
7.2.7.3. TCON Global Interrupt Register1 (Default Value: 0x0000_0000) ................................................. 434
7.2.7.4. TCON1 Control Register (Default Value: 0x0000_0000) ............................................................... 435
7.2.7.5. TCON1 Basic Timing Register0 (Default Value: 0x0000_0000) ..................................................... 435
7.2.7.6. TCON1 Basic Timing Register1 (Default Value: 0x0000_0000) ..................................................... 435
7.2.7.7. TCON1 Basic Timing Register2 (Default Value: 0x0000_0000) ..................................................... 436
7.2.7.8. TCON1 Basic Timing Register3 (Default Value: 0x0000_0000) ..................................................... 436
7.2.7.9. TCON1 Basic Timing Register (Default Value: 0x0000_0000) ....................................................... 436
7.2.7.10. TCON1 Basic Timing Register5 (Default Value: 0x0000_0000) ................................................... 436
7.2.7.11. TCON1 SYNC Register (Default Value: 0x0000_0000) ................................................................ 437
7.2.7.12. TCON1 IO Polarity Register (Default Value: 0x0000_0000) ........................................................ 437
7.2.7.13. TCON1 IO Trigger Register (Default Value: 0x0FFF_FFFF)........................................................... 438
7.2.7.14. TCON ECC FIFO Register (Default Value: UDF) ............................................................................ 438
7.2.7.15. TCON CEU Control Register (Default Value: 0x0000_0000) ....................................................... 439
7.2.7.16. TCON CEU Coefficient MUL Register (Default Value: 0x0000_0000) ......................................... 439
7.2.7.17. TCON CEU Coefficient Add Register (Default Value: 0x0000_0000) ........................................... 439
7.2.7.18. TCON CEU Coefficient Rang Register (Default Value: 0x0000_0000) ......................................... 440
7.2.7.19. TCON Safe Period Register (Default Value: 0x0000_0000) ......................................................... 440
7.2.7.20. TCON1 Fill Control Register (Default Value: 0x0000_0000) ....................................................... 440
7.2.7.21. TCON1 Fill Begin Register (Default Value: 0x0000_0000) .......................................................... 441
7.2.7.22. TCON1 Fill End Register (Default Value: 0x0000_0000) ............................................................. 441
7.2.7.23. TCON1 Fill Data Register (Default Value: 0x0000_0000) ............................................................ 441
Chapter 8 Audio ............................................................................................................................................................. 442
8.1. Audio Codec ....................................................................................................................................................... 443
8.1.1. Overview ................................................................................................................................................. 443
8.1.2. Block Diagram ......................................................................................................................................... 443
8.1.3. Operations and Functional Descriptions ................................................................................................. 444
8.1.3.1. External Signals ............................................................................................................................ 444
8.1.3.2. Clock Sources................................................................................................................................ 445
8.1.3.3. Reset System ................................................................................................................................ 445
8.1.3.4. Power Domain .............................................................................................................................. 446
8.1.4. Register List ............................................................................................................................................. 447
8.1.5. Register Description ................................................................................................................................ 450
8.1.5.1. 0x00 DAC Digital Part Control Register(Default Value: 0x0000_0000) ......................................... 450
8.1.5.2. 0x04 DAC FIFO Control Register (Default Value: 0x0000_4000) .................................................. 451
8.1.5.3. 0x08 DAC FIFO Status Register(Default Value: 0x0080_0088) ..................................................... 453
8.1.5.4. 0x10 ADC FIFO Control Register(Default Value: 0x0000_0F00) ................................................... 454
8.1.5.5. 0x14 ADC FIFO Status Register (Default Value: 0x0000_0000) .................................................... 456
8.1.5.6. 0x18 ADC RX DATA Register (Default Value: 0x0000_0000) ......................................................... 457
8.1.5.7. 0x20 DAC TX DATA Register (Default Value: 0x0000_0000) ......................................................... 457
8.1.5.8. 0x40 DAC TX Counter Register(Default Value: 0x0000_0000)...................................................... 457
8.1.5.9. 0x44 ADC RX Counter Register(Default Value: 0x0000_0000) ..................................................... 457
8.1.5.10. 0x48 DAC Debug Register (Default Value: 0x0000_0000) .......................................................... 458
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