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首页全志H5芯片详细参数与功能解析
全志H5芯片详细参数与功能解析
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"全志H5数据手册提供了关于全志公司H系列芯片中H5的详细技术参数和功能介绍。这是一款四核OTT盒处理器,适用于智能电视盒子等设备。"
全志H5芯片是一款高性能的四核心处理器,设计用于OTT(Over-The-Top)盒子应用,这意味着它专为通过互联网提供流媒体电视、视频和其他内容的设备而设计。这款芯片的发布日期为2016年5月,其数据手册(Revision 1.0)是全志科技的原创作品并受到版权保护。
在功能方面,全志H5可能包含了以下关键技术特性:
1. **四核心架构**:H5芯片采用多核处理器架构,可能包含四个ARM Cortex-A53 CPU核心,这种架构在能效和性能之间取得平衡,适用于处理多媒体任务和运行多应用程序。
2. **图形处理单元(GPU)**:为了支持高清视频播放和复杂的图形处理,H5可能集成了高性能的GPU,例如ARM的Mali系列,能够处理4K超高清分辨率的内容,支持OpenGL ES和OpenVG等图形标准。
3. **多媒体解码器**:全志H5可能内置了高效的视频解码硬件,能够支持多种编码格式,如H.265 (HEVC)、H.264、VP9等,确保流畅的高清视频体验。
4. **内存和存储接口**:H5芯片可能配备了高速DDR内存接口和eMMC或SD卡存储控制器,以提供快速的数据交换和大容量的存储空间。
5. **连接性**:考虑到OTT应用的需求,H5可能集成了Wi-Fi和蓝牙模块,支持无线网络连接和外设配对,同时也可能包含有线网络接口如以太网控制器。
6. **电源管理**:高效能的电源管理单元(PMU)是必不可少的,确保设备在不同工作状态下的功耗控制,延长电池寿命。
7. **I/O接口**:H5可能提供多种接口,如HDMI、USB、UART和GPIO,以便连接各种外部设备,如显示器、遥控器、硬盘和网络适配器。
8. **安全性**:由于涉及内容分发和用户隐私,全志H5可能会包含安全特性,如硬件加密引擎,以确保数据传输和存储的安全。
值得注意的是,全志科技声明该数据手册提供的信息虽然被认为是准确和可靠的,但不保证无误,且保留随时更改设计和规格的权利。使用该芯片可能需要第三方许可,并且不提供任何明示或暗示的保修。此外,用户应自行承担使用可能引发的专利侵权或其他第三方权利侵犯的责任。
全志H5芯片是一个强大的解决方案,旨在为OTT盒子提供高效能的计算能力和多媒体处理能力,满足现代家庭娱乐系统的需求。然而,实际应用时需要结合具体产品设计和第三方软件配合,确保兼容性和性能优化。
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 16
4.22.3.8. PL PULL Register 0 (Default Value: 0x0000_0005) ..................................................................... 328
4.22.3.9. PL PULL Register 1 (Default Value: 0x0000_0000) ..................................................................... 328
4.22.3.10. PL External Interrupt Configure Register 0 (Default Value: 0x0000_0000) .............................. 328
4.22.3.11. PL External Interrupt Configure Register 1 (Default Value: 0x0000_0000) .............................. 328
4.22.3.12. PL External Interrupt Configure Register 2 (Default Value: 0x0000_0000) .............................. 329
4.22.3.13. PL External Interrupt Configure Register 3 (Default Value: 0x0000_0000) .............................. 329
4.22.3.14. PL External Interrupt Control Register (Default Value: 0x0000_0000) ..................................... 329
4.22.3.15. PL External Interrupt Status Register (Default Value: 0x0000_0000) ....................................... 329
4.22.3.16. PL External Interrupt Debounce Register (Default Value: 0x0000_0000) ................................ 330
Chapter 5 Memory ......................................................................................................................................................... 331
5.1. SDRAM Controller(DRAMC) ............................................................................................................................... 332
5.1.1. Overview ................................................................................................................................................. 332
5.2. NAND Flash Controller(NDFC) ............................................................................................................................ 333
5.2.1. Overview ................................................................................................................................................. 333
5.2.2. Block Diagram ......................................................................................................................................... 333
5.2.3. Operations and Functional Descriptions ................................................................................................. 334
5.2.3.1. External Signals ............................................................................................................................ 334
5.2.3.2. Clock Sources................................................................................................................................ 335
5.2.3.3. NDFC Timing Diagram .................................................................................................................. 335
5.2.3.4. NDFC Operation Guide ................................................................................................................. 341
5.2.4. Register List ............................................................................................................................................. 343
5.2.5. Register Description ................................................................................................................................ 344
5.2.5.1. NDFC Control Register (Default Value: 0x0000_0000) ................................................................. 344
5.2.5.2. NDFC Status Register (Default Value: 0x0000_0F00) ................................................................... 346
5.2.5.3. NDFC Interrupt and DMA Enable Register (Default Value: 0x0000_0000) ................................... 347
5.2.5.4. NDFC Timing Control Register (Default Value: 0x0000_0000) ..................................................... 348
5.2.5.5. NDFC Timing Configure Register (Default Value: 0x0000_0095) ................................................. 348
5.2.5.6. NDFC Address Low Word Register (Default Value: 0x0000_0000) ............................................... 350
5.2.5.7. NDFC Address High Word Register (Default Value: 0x0000_0000) .............................................. 350
5.2.5.8. NDFC Data Block Number Register (Default Value: 0x0000_0000) .............................................. 351
5.2.5.9. NDFC Data Counter Register (Default Value: 0x0000_0000) ........................................................ 351
5.2.5.10. NDFC Command IO Register (Default Value: 0x0000_0000) ...................................................... 351
5.2.5.11. NDFC Command Set Register 0 (Default Value: 0x00E0_0530).................................................. 353
5.2.5.12. NDFC Command Set Register 1 (Default Value: 0x7000_8510).................................................. 354
5.2.5.13. NDFC ECC Control Register (Default Value: 0x4A80_0008) ........................................................ 354
5.2.5.14. NDFC ECC Status Register (Default Value: 0x0000_0000) .......................................................... 355
5.2.5.15. NDFC Enhanced Feature Register (Default Value: 0x0000_0000) .............................................. 356
5.2.5.16. NDFC Error Counter Register 0 (Default Value: 0x0000_0000) .................................................. 356
5.2.5.17. NDFC Error Counter Register 1 (Default Value: 0x0000_0000) .................................................. 357
5.2.5.18. NDFC Error Counter Register 2 (Default Value: 0x0000_0000) .................................................. 359
5.2.5.19. NDFC Error Counter Register 3 (Default Value: 0x0000_0000) .................................................. 360
5.2.5.20. NDFC User Data Register [N] (Default Value: 0xFFFF_FFFF) ....................................................... 361
5.2.5.21. NDFC EFNAND STATUS Register (Default Value: 0x0000_0000) ................................................. 361
5.2.5.22. NDFC Spare Area Register (Default Value: 0x0000_0400) .......................................................... 361
5.2.5.23. NDFC Pattern ID Register (Default Value: 0x0000_0000) ........................................................... 361
5.2.5.24. NDFC Read Data Status Control Register (Default Value: 0x0100_0000) ................................... 364
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 17
5.2.5.25. NDFC Read Data Status Register 0 (Default Value: 0x0000_0000) ............................................. 364
5.2.5.26. NDFC Read Data Status Register 1 (Default Value: 0x0000_0000) ............................................. 364
5.2.5.27. NDFC MBUS DMA Address Register (Default Value: 0x0000_0000) .......................................... 365
5.2.5.28. NDFC MBUS DMA Byte Counter Register (Default Value: 0x0000_0000) .................................. 365
5.2.5.29. NDFC Normal DMA Mode Control Register (Default Value: 0x0000_00A5) .............................. 365
5.2.5.30. NDFC IO Data Register (Default Value: 0x0000_0000) ............................................................... 365
5.3. SD/MMC Host Controller(SMHC) ....................................................................................................................... 366
5.3.1. Overview ................................................................................................................................................. 366
5.3.2. Block Diagram ......................................................................................................................................... 366
5.3.3. Operations and Functional Descriptions ................................................................................................. 367
5.3.3.1. External Signals ............................................................................................................................ 367
5.3.3.2. Clock Sources................................................................................................................................ 367
5.3.3.3. SMHC Timing Diagram ................................................................................................................. 367
5.3.3.4. Internal DMA Controller Description ........................................................................................... 368
5.3.3.5. Calibrate Delay Chain ................................................................................................................... 370
5.3.4. Register List ............................................................................................................................................. 370
5.3.5. Register Description ................................................................................................................................ 372
5.3.5.1. SMHC Global Control Register (Default Value: 0x0000_0100) ..................................................... 372
5.3.5.2. SMHC Clock Control Register (Default Value: 0x0000_0000) ....................................................... 373
5.3.5.3. SMHC Timeout Register (Default Value: 0xFFFF_FF40)................................................................ 374
5.3.5.4. SMHC Bus Width Register (Default Value: 0x0000_0000) ........................................................... 374
5.3.5.5. SMHC Block Size Register (Default Value: 0x0000_0200) ............................................................ 374
5.3.5.6. SMHC Block Count Register (Default Value: 0x0000_0200) ......................................................... 374
5.3.5.7. SMHC Command Register (Default Value: 0x0000_0000)............................................................ 375
5.3.5.8. SMHC Command Argument Register (Default Value: 0x0000_0000) .......................................... 377
5.3.5.9. SMHC Response 0 Register (Default Value: 0x0000_0000) .......................................................... 377
5.3.5.10. SMHC Response 1 Register (Default Value: 0x0000_0000) ........................................................ 377
5.3.5.11. SMHC Response 2 Register (Default Value: 0x0000_0000) ........................................................ 377
5.3.5.12. SMHC Response 3 Register (Default Value: 0x0000_0000) ........................................................ 378
5.3.5.13. SMHC Interrupt Mask Register (Default Value: 0x0000_0000) .................................................. 378
5.3.5.14. SMHC Masked Interrupt Status Register (Default Value: 0x0000_0000) ................................... 379
5.3.5.15. SMHC Raw Interrupt Status Register (Default Value: 0x0000_0000) ......................................... 380
5.3.5.16. SMHC Status Register (Default Value: 0x0000_0006) ................................................................ 382
5.3.5.17. SMHC FIFO Water Level Register (Default Value: 0x000F_0000) ............................................... 383
5.3.5.18. SMHC Function Select Register (Default Value: 0x0000_0000) ................................................. 384
5.3.5.19. SMHC Transferred Byte Count Register0 (Default Value: 0x0000_0000) ................................... 385
5.3.5.20. SMHC Transferred Byte Count Register1 (Default Value: 0x0000_0000) ................................... 385
5.3.5.21. SMHC Auto Command 12 Argument Register (Default Value: 0x0000_FFFF) ............................ 386
5.3.5.22. SMHC New Timing Set Register (Default Value: 0x8171_0000) ................................................. 386
5.3.5.23. SMHC Hardware Reset Register (Default Value: 0x0000_0001) ................................................. 387
5.3.5.24. SMHC DMAC Control Register (Default Value: 0x0000_0000) ................................................... 387
5.3.5.25. SMHC Descriptor List Base Address Register (Default Value: 0x0000_0000) ............................. 388
5.3.5.26. SMHC DMAC Status Register (Default Value: 0x0000_0000) ..................................................... 389
5.3.5.27. SMHC DMAC Interrupt Enable Register (Default Value: 0x0000_0000) ..................................... 390
5.3.5.28. SMHC Current Host Descriptor Address Register (Default Value: 0x0000_0000) ...................... 391
5.3.5.29. SMHC Current Buffer Descriptor Address Register (Default Value: 0x0000_0000) .................... 391
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 18
5.3.5.30. SMHC Card Threshold Control Register (Default Value: 0x0000_0000) ..................................... 392
5.3.5.31. SMHC eMMC4.5 DDR Start Bit Detection Control Register (Default Value: 0x0000_0000) ....... 392
5.3.5.32. SMHC Response CRC Register (Default Value: 0x0000_0000) ................................................... 393
5.3.5.33. SMHC Data7 CRC Register (Default Value: 0x0000_0000) ......................................................... 393
5.3.5.34. SMHC Data6 CRC Register (Default Value: 0x0000_0000) ......................................................... 394
5.3.5.35. SMHC Data5 CRC Register (Default Value: 0x0000_0000) ......................................................... 394
5.3.5.36. SMHC Data4 CRC Register (Default Value: 0x0000_0000) ......................................................... 394
5.3.5.37. SMHC Data3 CRC Register (Default Value: 0x0000_0000) ......................................................... 395
5.3.5.38. SMHC Data2 CRC Register (Default Value: 0x0000_0000) ......................................................... 395
5.3.5.39. SMHC Data1 CRC Register (Default Value: 0x0000_0000) ......................................................... 395
5.3.5.40. SMHC Data0 CRC Register (Default Value: 0x0000_0000) ......................................................... 396
5.3.5.41. SMHC CRC Status Register (Default Value: 0x0000_0000) ......................................................... 396
5.3.5.42. SMHC Drive Delay Control Register (Default Value: 0x0001_0000) ........................................... 396
5.3.5.43. SMHC Sample Delay Control Register (Default Value: 0x0000_2000) ........................................ 397
5.3.5.44. SMHC Data Strobe Delay Control Register (Default Value: 0x0000_2000) ................................ 397
5.3.5.45. SMHC FIFO Register (Default Value: 0x0000_0000) ................................................................... 398
Chapter 6 Image ............................................................................................................................................................. 399
6.1. CSI....................................................................................................................................................................... 400
6.1.1. Overview ................................................................................................................................................. 400
6.1.2. Block Diagram ......................................................................................................................................... 401
6.1.3. Operations and Functional Descriptions ................................................................................................. 402
6.1.3.1. CSI FIFO Distribution .................................................................................................................... 402
6.1.3.2. CSI Timing..................................................................................................................................... 402
6.1.3.3. Bit Definition ................................................................................................................................ 403
6.1.4. Register list .............................................................................................................................................. 403
6.1.5. Register Description ................................................................................................................................ 404
6.1.5.1. CSI Enable Register (Default Value: 0x0000_0000) ...................................................................... 404
6.1.5.2. CSI Interface Configuration Register (Default Value: 0x0005_0000) ............................................ 405
6.1.5.3. CSI Capture Register (Default Value: 0x0000_0000) .................................................................... 407
6.1.5.4. CSI Synchronization Counter Register (Default Value: 0x0000_0000) ......................................... 407
6.1.5.5. CSI FIFO Threshold Register (Default Value: 0x040F_0400) ......................................................... 408
6.1.5.6. CSI Pattern Generation Length Register (Default Value: 0x0000_0000) ...................................... 408
6.1.5.7. CSI Pattern Generation Address Register (Default Value: 0x0000_0000) .................................... 408
6.1.5.8. CSI Version Register (Default Value: 0x0000_0000) ..................................................................... 408
6.1.5.9. CSI Channel_0 Configuration Register (Default Value: 0x0030_0200) ......................................... 409
6.1.5.10. CSI Channel_0 Scale Register (Default Value: 0x0000_0000) ..................................................... 411
6.1.5.11. CSI Channel_0 FIFO 0 Output Buffer-A Address Register (Default Value: 0x0000_0000) .......... 411
6.1.5.12. CSI Channel_0 FIFO 1 Output Buffer-A Address Register (Default Value: 0x0000_0000) .......... 411
6.1.5.13. CSI Channel_0 FIFO 2 Output Buffer-A Address Register (Default Value: 0x0000_0000) .......... 412
6.1.5.14. CSI Channel_0 Status Register (Default Value: 0x0000_0000) ................................................... 412
6.1.5.15. CSI Channel_0 Interrupt Enable Register (Default Value: 0x0000_0000)................................... 412
6.1.5.16. CSI Channel_0 Interrupt Status Register (Default Value: 0x0000_0000) ................................... 413
6.1.5.17. CSI Channel_0 Horizontal Size Register (Default Value: 0x0500_0000) ..................................... 414
6.1.5.18. CSI Channel_0 Vertical Size Register (Default Value: 0x01E0_0000) .......................................... 414
6.1.5.19. CSI Channel_0 Buffer Length Register (Default Value: 0x0140_0280) ....................................... 414
6.1.5.20. CSI Channel_0 Flip Size Register (Default Value: 0x01E0_0280) ................................................ 415
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 19
6.1.5.21. CSI Channel_0 Frame Clock Counter Register (Default Value: 0x0000_0000) ........................... 415
6.1.5.22. CSI Channel_0 accumulated and internal clock counter Register (Default Value: 0x0000_0000)
................................................................................................................................................................... 415
6.1.5.23. CSI Channel_0 FIFO Statistic Register (Default Value: 0x0000_0000) ........................................ 415
6.1.5.24. CSI Channel_0 PCLK Statistic Register (Default Value: 0x0000_7FFF) ........................................ 416
6.1.5.25. CCI Control Register (Default Value: 0x0000_0000) ................................................................... 416
6.1.5.26. CCI Transmission Configuration Register (Default Value: 0x1000_0000) ................................... 418
6.1.5.27. CCI Packet Format Register (Default Value: 0x0011_0001) ........................................................ 418
6.1.5.28. CCI Bus Control Register (Default Value: 0x0000_2500) ............................................................ 419
6.1.5.29. CCI Interrupt Control Register (Default Value: 0x0000_0000) ................................................... 420
6.1.5.30. CCI Line Counter Trigger Control Register (Default Value: 0x0000_0000) ................................. 420
6.1.5.31. CCI FIFO Access Register (Default Value: 0x0000_0000) ............................................................ 420
Chapter 7 Display ........................................................................................................................................................... 421
7.1. DE2.0 .................................................................................................................................................................. 422
7.1.1. Overview ................................................................................................................................................. 422
7.2. TCON .................................................................................................................................................................. 423
7.2.1. Overview ................................................................................................................................................. 423
7.2.2. Block Diagram ......................................................................................................................................... 423
7.2.3. Operations and Functional Descriptions ................................................................................................. 423
7.2.3.1. RGB Gamma Correction ............................................................................................................... 423
7.2.3.2. CEU Module ................................................................................................................................. 424
7.2.4. TCON0 Module Register List ................................................................................................................... 424
7.2.5. TCON0 Module Register Description ...................................................................................................... 425
7.2.5.1. TCON Global Control Register (Default Value: 0x0000_0000) ...................................................... 425
7.2.5.2. TCON Global Interrupt Register0 (Default Value: 0x0000_0000) ................................................. 425
7.2.5.3. TCON Global Interrupt Register1 (Default Value: 0x0000_0000) ................................................. 426
7.2.5.4. TCON1 Control Register (Default Value: 0x0000_0000) ............................................................... 426
7.2.5.5. TCON1 Basic Timing Register0 (Default Value: 0x0000_0000) ..................................................... 426
7.2.5.6. TCON1 Basic Timing Register1 (Default Value: 0x0000_0000) ..................................................... 427
7.2.5.7. TCON1 Basic Timing Register2 (Default Value: 0x0000_0000) ..................................................... 427
7.2.5.8. TCON1 Basic Timing Register3 (Default Value: 0x0000_0000) ..................................................... 427
7.2.5.9. TCON1 Basic Timing Register4 (Default Value: 0x0000_0000) ..................................................... 428
7.2.5.10. TCON1 Basic Timing Register5 (Default Value: 0x0000_0000) ................................................... 428
7.2.5.11. TCON1 SYNC Register (Default Value: 0x0000_0000) ................................................................ 428
7.2.5.12. TCON1 IO Polarity Register (Default Value: 0x0000_0000) ........................................................ 428
7.2.5.13. TCON1 IO Trigger Register (Default Value: 0x0FFF_FFFF)........................................................... 429
7.2.5.14. TCON ECC FIFO Register (Default Value: UDF) ............................................................................ 430
7.2.5.15. TCON CEU Control Register (Default Value: 0x0000_0000) ....................................................... 430
7.2.5.16. TCON CEU Coefficient MUL Register (Default Value: 0x0000_0000) ......................................... 430
7.2.5.17. TCON CEU Coefficient Add Register (Default Value: 0x0000_0000) ........................................... 431
7.2.5.18. TCON CEU Coefficient Range Register (Default Value: 0x0000_0000) ....................................... 431
7.2.5.19. TCON Safe Period Register (Default Value: 0x0000_0000) ......................................................... 431
7.2.5.20. TCON1 Fill Control Register (Default Value: 0x0000_0000) ....................................................... 432
7.2.5.21. TCON1 Fill Begin Register (Default Value: 0x0000_0000) .......................................................... 432
7.2.5.22. TCON1 Fill End Register (Default Value: 0x0000_0000) ............................................................. 432
7.2.5.23. TCON1 Fill Data Register (Default Value: 0x0000_0000) ............................................................ 432
Table of Contents
H5 Datasheet(Revision 1.0) Copyright© 2016 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 20
7.2.6. TCON1 Module Register List ................................................................................................................... 433
7.2.7. TCON1 Module Register Description ...................................................................................................... 433
7.2.7.1. TCON Global Control Register (Default Value: 0x0000_0000) ...................................................... 433
7.2.7.2. TCON Global Interrupt Register0 (Default Value: 0x0000_0000) ................................................. 434
7.2.7.3. TCON Global Interrupt Register1 (Default Value: 0x0000_0000) ................................................. 434
7.2.7.4. TCON1 Control Register (Default Value: 0x0000_0000) ............................................................... 435
7.2.7.5. TCON1 Basic Timing Register0 (Default Value: 0x0000_0000) ..................................................... 435
7.2.7.6. TCON1 Basic Timing Register1 (Default Value: 0x0000_0000) ..................................................... 435
7.2.7.7. TCON1 Basic Timing Register2 (Default Value: 0x0000_0000) ..................................................... 436
7.2.7.8. TCON1 Basic Timing Register3 (Default Value: 0x0000_0000) ..................................................... 436
7.2.7.9. TCON1 Basic Timing Register (Default Value: 0x0000_0000) ....................................................... 436
7.2.7.10. TCON1 Basic Timing Register5 (Default Value: 0x0000_0000) ................................................... 436
7.2.7.11. TCON1 SYNC Register (Default Value: 0x0000_0000) ................................................................ 437
7.2.7.12. TCON1 IO Polarity Register (Default Value: 0x0000_0000) ........................................................ 437
7.2.7.13. TCON1 IO Trigger Register (Default Value: 0x0FFF_FFFF)........................................................... 438
7.2.7.14. TCON ECC FIFO Register (Default Value: UDF) ............................................................................ 438
7.2.7.15. TCON CEU Control Register (Default Value: 0x0000_0000) ....................................................... 439
7.2.7.16. TCON CEU Coefficient MUL Register (Default Value: 0x0000_0000) ......................................... 439
7.2.7.17. TCON CEU Coefficient Add Register (Default Value: 0x0000_0000) ........................................... 439
7.2.7.18. TCON CEU Coefficient Rang Register (Default Value: 0x0000_0000) ......................................... 440
7.2.7.19. TCON Safe Period Register (Default Value: 0x0000_0000) ......................................................... 440
7.2.7.20. TCON1 Fill Control Register (Default Value: 0x0000_0000) ....................................................... 440
7.2.7.21. TCON1 Fill Begin Register (Default Value: 0x0000_0000) .......................................................... 441
7.2.7.22. TCON1 Fill End Register (Default Value: 0x0000_0000) ............................................................. 441
7.2.7.23. TCON1 Fill Data Register (Default Value: 0x0000_0000) ............................................................ 441
Chapter 8 Audio ............................................................................................................................................................. 442
8.1. Audio Codec ....................................................................................................................................................... 443
8.1.1. Overview ................................................................................................................................................. 443
8.1.2. Block Diagram ......................................................................................................................................... 443
8.1.3. Operations and Functional Descriptions ................................................................................................. 444
8.1.3.1. External Signals ............................................................................................................................ 444
8.1.3.2. Clock Sources................................................................................................................................ 445
8.1.3.3. Reset System ................................................................................................................................ 445
8.1.3.4. Power Domain .............................................................................................................................. 446
8.1.4. Register List ............................................................................................................................................. 447
8.1.5. Register Description ................................................................................................................................ 450
8.1.5.1. 0x00 DAC Digital Part Control Register(Default Value: 0x0000_0000) ......................................... 450
8.1.5.2. 0x04 DAC FIFO Control Register (Default Value: 0x0000_4000) .................................................. 451
8.1.5.3. 0x08 DAC FIFO Status Register(Default Value: 0x0080_0088) ..................................................... 453
8.1.5.4. 0x10 ADC FIFO Control Register(Default Value: 0x0000_0F00) ................................................... 454
8.1.5.5. 0x14 ADC FIFO Status Register (Default Value: 0x0000_0000) .................................................... 456
8.1.5.6. 0x18 ADC RX DATA Register (Default Value: 0x0000_0000) ......................................................... 457
8.1.5.7. 0x20 DAC TX DATA Register (Default Value: 0x0000_0000) ......................................................... 457
8.1.5.8. 0x40 DAC TX Counter Register(Default Value: 0x0000_0000)...................................................... 457
8.1.5.9. 0x44 ADC RX Counter Register(Default Value: 0x0000_0000) ..................................................... 457
8.1.5.10. 0x48 DAC Debug Register (Default Value: 0x0000_0000) .......................................................... 458
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