没有合适的资源?快使用搜索试试~ 我知道了~
首页Allwinner F1C600 用户手册 v1.0:版权与声明
Allwinner F1C600 用户手册 v1.0:版权与声明
需积分: 1 0 下载量 170 浏览量
更新于2024-06-14
收藏 9.72MB PDF 举报
Allwinner-F1C600-User-Manual-V1.0 是一份关于Allwinner Technology Co., Ltd. 的产品用户手册,修订于2015年11月10日。这份文档是该公司的原创作品,受到版权保护。手册包含了关于F1C600芯片的详细信息和操作指南,强调了未经Allwinner书面许可,任何形式的复制或部分复制都必须得到明确的认可。 在文档的声明部分,用户被明确告知此文档是Allwinner的原始知识产权,不得擅自复制或传播,除非得到Allwinner的书面许可,并且在使用过程中必须承认Allwinner作为版权所有者。手册中的信息被认为是准确可靠的,但Allwinner保留随时更改电路设计和规格的权利,无需提前通知用户。 值得注意的是,Allwinner并不承担因使用该手册而导致的任何责任,包括侵犯第三方专利权或其他权益的情况。用户在使用F1C600时需自行承担风险,因为手册并未授予任何专利使用权,也不保证产品的特定应用适用性。此外,可能需要第三方许可才能实现某些解决方案或产品功能。 这份用户手册并不构成任何形式的保修,无论是针对性能还是特定用途的适用性。这意味着用户在接收和使用F1C600芯片时,需要自行评估其适用性和兼容性,同时可能需要获取额外的技术支持和指导,以确保遵循Allwinner的建议和最佳实践。 Allwinner-F1C600-User-Manual-V1.0 是针对Allwinner F1C600芯片的专业技术文档,提供芯片的基本信息、操作指南以及重要的法律声明和免责声明,对开发者和使用者了解和使用该芯片具有关键参考价值。
资源详情
资源推荐
Revision History
F1C600 User Manual (Revision 1.0) Copyright© 2015 Allwinner Technology. Co.,Ltd. All Rights Reserved. Page 16
4.2.5. Operation Mode ...................................................................................................................................... 146
4.2.5.1. Basic principle .............................................................................................................................. 146
4.2.5.2. Single-ended mode ...................................................................................................................... 146
4.2.5.3. Differential mode ......................................................................................................................... 147
4.2.5.4. Single touch detection ................................................................................................................. 147
4.2.5.5. Dual touch detection .................................................................................................................... 148
4.2.5.6. Touch pressure measurement ...................................................................................................... 148
4.2.5.7. Pen down detection, with programmable sensitivity .................................................................. 149
4.2.5.8. Median and averaging filter ......................................................................................................... 150
4.2.6. TP Register List ........................................................................................................................................ 151
4.2.7. TP Register Description ........................................................................................................................... 151
4.2.7.1. TP Control Register 0 .................................................................................................................... 151
4.2.7.2. TP Control Register 1 .................................................................................................................... 152
4.2.7.3. TP Control Register 2 .................................................................................................................... 153
4.2.7.4. TP Control Register 3
.................................................................................................................... 154
4.2.7.5. TP Interrupt FIFO Control Register ............................................................................................... 154
4.2.7.6. TP Interrupt FIFO Status Register ................................................................................................. 155
4.2.7.7. TP Common Data Register ............................................................................................................ 156
4.2.7.8. TP Data Register ........................................................................................................................... 156
4.3. Audio Codec ....................................................................................................................................................... 157
4.3.1. Overview ................................................................................................................................................. 157
4.3.2. Feature .................................................................................................................................................... 157
4.3.3. Block diagram .......................................................................................................................................... 157
4.3.4. Signal Description .................................................................................................................................... 157
Confidential
Revision History
F1C600 User Manual (Revision 1.0) Copyright© 2015 Allwinner Technology. Co.,Ltd. All Rights Reserved. Page 17
4.3.5. Power Description ................................................................................................................................... 158
4.3.6. Function Description ............................................................................................................................... 158
4.3.6.1. ADC ............................................................................................................................................... 158
4.3.6.2. Stereo ADC ................................................................................................................................... 158
4.3.6.3. Mixer ............................................................................................................................................ 158
4.3.6.4. Headphone Mixer ......................................................................................................................... 158
4.3.6.5. ADC Record Mixer ........................................................................................................................ 158
4.3.6.6. Analog Audio Input Path .............................................................................................................. 159
4.3.6.7. FM Input ....................................................................................................................................... 159
4.3.7. Audio Codec Register List ........................................................................................................................ 160
4.3.8. Audio Codec Register Description ........................................................................................................... 160
4.3.8.1. DAC Digital Part Control Register ................................................................................................. 160
4.3.8.2. DAC FIFO Control Register ............................................................................................................ 162
4.3.8.3. DAC FIFO Status Register .............................................................................................................. 164
4.3.8.4. DAC TX DATA Register ................................................................................................................... 164
4.3.8.5. ADC FIFO Control Register ............................................................................................................ 165
4.3.8.6. ADC FIFO Status Register .............................................................................................................. 166
4.3.8.7. ADC RX DATA Register .................................................................................................................. 167
4.3.8.8. DAC Analog & Output MIXER Control Register ............................................................................ 167
4.3.8.9. ADC Analog and Input mixer Control Register ............................................................................. 169
4.3.8.10. ADC&DAC performance tuning Register .................................................................................... 170
4.3.8.11. Bias & DA16 Calibration Control Register 0 ................................................................................ 171
4.3.8.12. Bias & DA16 Calibration Control Register 1 ................................................................................ 172
4.3.8.13. DAC TX Counter Register ............................................................................................................ 172
Confidential
Revision History
F1C600 User Manual (Revision 1.0) Copyright© 2015 Allwinner Technology. Co.,Ltd. All Rights Reserved. Page 18
4.3.8.14. ADC RX Counter Register ............................................................................................................ 172
4.3.8.15. DAC Debug Register ................................................................................................................... 172
4.3.8.16. ADC Debug Register ................................................................................................................... 173
4.3.8.17. ADC DAP Control Register .......................................................................................................... 173
4.3.8.18. ADC DAP Left Control Register ................................................................................................... 174
4.3.8.19. ADC DAP Right Control Register ................................................................................................. 175
4.3.8.20. ADC DAP Parameter Register ..................................................................................................... 176
4.3.8.21. ADC DAP Left Average Coef Register .......................................................................................... 177
4.3.8.22. ADC DAP Left Decay & Attack Time Register .............................................................................. 177
4.3.8.23. ADC DAP Right Average Coef Register ........................................................................................ 177
4.3.8.24. ADC DAP Right Decay & Attack Time Register ........................................................................... 178
4.3.8.25. ADC DAP HPF Coef Register ........................................................................................................ 178
4.3.8.26. ADC DAP Left Input Signal Low Average Coef Register ................................
.............................. 178
4.3.8.27. ADC DAP Right Input Signal Low Average Coef Register ............................................................ 178
4.3.8.28. ADC DAP Optimum Register ....................................................................................................... 179
Chapter 5. Display ............................................................................................................................................................. 180
5.1. TCON .................................................................................................................................................................. 181
5.1.1. Overview ................................................................................................................................................. 181
5.1.2. Feature .................................................................................................................................................... 181
5.1.3. Block Diagram ......................................................................................................................................... 181
5.1.3.1. LCD Timing Controller .................................................................................................................. 181
5.1.4. TCON Register List ................................................................................................................................... 182
5.1.5. TCON Register Description ...................................................................................................................... 183
5.1.5.1. TCON Control Register .................................................................................................................. 183
Confidential
Revision History
F1C600 User Manual (Revision 1.0) Copyright© 2015 Allwinner Technology. Co.,Ltd. All Rights Reserved. Page 19
5.1.5.2. TCON Interrupt Register 0 ............................................................................................................ 183
5.1.5.3. TCON Interrupt Register 1 ............................................................................................................ 184
5.1.5.4. TCON FRM Control Register ......................................................................................................... 184
5.1.5.5. TCON FRM Seed0 Red Register .................................................................................................... 184
5.1.5.6. TCON FRM Seed0 Green Register ................................................................................................. 184
5.1.5.7. TCON FRM Seed0 Blue Register ................................................................................................... 185
5.1.5.8. TCON FRM Seed1 Red Register .................................................................................................... 185
5.1.5.9. TCON FRM Seed1 Green Register ................................................................................................. 185
5.1.5.10. TCON FRM Seed1 Blue Register ................................................................................................. 185
5.1.5.11. TCON FRM Table Register 0 ........................................................................................................ 185
5.1.5.12. TCON FRM Table Register 1 ........................................................................................................ 185
5.1.5.13. TCON FRM Table Register 2 ........................................................................................................
186
5.1.5.14. TCON FRM Table Register 3 ........................................................................................................ 186
5.1.5.15. TCON0 Control Register .............................................................................................................. 186
5.1.5.16. TCON Clock Control Register ...................................................................................................... 187
5.1.5.17. TCON0 Basic Timing Register 0 .................................................................................................. 187
5.1.5.18. TCON0 Basic Timing Register 1 .................................................................................................. 187
5.1.5.19. TCON0 Basic Timing Register 2 .................................................................................................. 188
5.1.5.20. TCON0 Basic Timing Register 3 .................................................................................................. 188
5.1.5.21. TCON0 HV Timing Register ......................................................................................................... 188
5.1.5.22. TCON0 CPU Interface Control Register ....................................................................................... 189
5.1.5.23. TCON0 CPU Write Register ......................................................................................................... 190
5.1.5.24. TCON0 CPU Read Register .......................................................................................................... 190
5.1.5.25. TCON0 CPU Read NX Register
.................................................................................................... 190
Confidential
Revision History
F1C600 User Manual (Revision 1.0) Copyright© 2015 Allwinner Technology. Co.,Ltd. All Rights Reserved. Page 20
5.1.5.26. TCON0 IO Control Register 0 ...................................................................................................... 190
5.1.5.27. TCON0 IO Control Register 1 ...................................................................................................... 191
5.1.5.28. TCON1 Control Register .............................................................................................................. 191
5.1.5.29. TCON1 Basic Timing Register 0 .................................................................................................. 192
5.1.5.30. TCON1 Basic Timing Register 1 .................................................................................................. 192
5.1.5.31. TCON1 Basic Timing Register 2 .................................................................................................. 192
5.1.5.32. TCON1 Basic Timing Register 3 .................................................................................................. 193
5.1.5.33. TCON1 Basic Timing Register 4 .................................................................................................. 193
5.1.5.34. TCON1 Basic Timing Register 5 .................................................................................................. 193
5.1.5.35. TCON1 IO Control Register 0 ...................................................................................................... 193
5.1.5.36. TCON1 IO Control Register 1 ...................................................................................................... 194
5.1.5.37. TCON Debug Information Register ............................................................................................. 194
5.2. Display Engine Front-End ................................................................................................................................... 196
5.2.1. Overview ................................................................................................................................................. 196
5.2.2. Feature .................................................................................................................................................... 196
5.2.3. Block Diagram ......................................................................................................................................... 196
5.2.4. DEFE Register List .................................................................................................................................... 196
5.2.5. DEFE Register Description ....................................................................................................................... 198
5.2.5.1. DEFE Module Enable Register ...................................................................................................... 198
5.2.5.2. DEFE Frame Process Control Register .......................................................................................... 198
5.2.5.3. DEFE CSC Bypass Register ............................................................................................................. 199
5.2.5.4. DEFE Algorithm Selection Register ............................................................................................... 200
5.2.5.5. DEFE Line Interrupt Conrtol Register............................................................................................ 200
5.2.5.6. DEFE Input Channel 0 Buffer Address Register ............................................................................ 200
Confidential
剩余356页未读,继续阅读
zhaihuaming
- 粉丝: 1
- 资源: 10
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
最新资源
- C++多态实现机制详解:虚函数与早期绑定
- Java多线程与异常处理详解
- 校园导游系统:无向图实现最短路径探索
- SQL2005彻底删除指南:避免重装失败
- GTD时间管理法:提升效率与组织生活的关键
- Python进制转换全攻略:从10进制到16进制
- 商丘物流业区位优势探究:发展战略与机遇
- C语言实训:简单计算器程序设计
- Oracle SQL命令大全:用户管理、权限操作与查询
- Struts2配置详解与示例
- C#编程规范与最佳实践
- C语言面试常见问题解析
- 超声波测距技术详解:电路与程序设计
- 反激开关电源设计:UC3844与TL431优化稳压
- Cisco路由器配置全攻略
- SQLServer 2005 CTE递归教程:创建员工层级结构
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功