PCIe M.2规格1.1版（2016年3月）：最新SSD标准

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PCIExpress M.2规格化是IT行业中的一个重要进展，它定义了高速接口标准用于现代计算机内部的M.2固态硬盘（SSD）连接。PCIe M.2 Specification Rev1.1，发布于2016年3月7日，标志着对前一代规范的更新和完善，旨在提供更快的数据传输速度和更高效的系统集成。这个规格的核心关注点在于PCI Express（PCIe）技术，这是一种广泛应用于计算机主板上的扩展槽，用于连接各种扩展卡，包括高性能存储设备。M.2标准允许SSD直接通过PCIe接口与主板连接，无需额外的扩展卡，从而显著减少了延迟和功耗，并提高了整体系统性能。在Rev1.1版本中，可能包含了以下关键特性： 1. 带宽提升：PCIe M.2接口支持更高的数据传输速率，比如PCIe 3.0或更高级别的标准，使得SSD的读写速度有了显著提升，对于需要处理大量数据的工作负载至关重要。 2. 物理尺寸与可扩展性：该规范定义了不同类型的M.2模块尺寸（如M-Key、B-Key等），以适应不同尺寸的SSD和不同的应用场景需求。 3. 热插拔和电源管理：新版本可能强化了M.2 SSD的热插拔功能和电源管理，确保在不同工作模式下能稳定运行且节能。 4. 错误检测与校验：为了提高数据可靠性，可能会包含更先进的错误检测和纠正机制，防止数据丢失。 5. 兼容性和互通性：PCI-SIG确保了各厂商设备之间的互操作性，以便消费者可以轻松更换不同品牌但遵循同一规格的M.2 SSD。 6. 持续更新：PCI-SIG强调文档可能存在错误，用户应获取最新修订版以获取最准确的信息，且声明不承诺更新内容，因此开发者和用户需保持关注以适应技术发展。如果你计划使用或开发基于PCIe M.2的SSD产品，理解并遵守这个规格的细节至关重要。通过了解其工作原理、接口标准以及潜在限制，你可以优化系统设计，提升用户体验，并确保与未来的硬件兼容。同时，如果在实施过程中遇到疑问，可通过PCI-SIG的官方联系方式寻求帮助和支持。

PCI Express M.2 Specification

PCI Express M.2 Specification | 16

Revision 1.1, March 7, 2016

List of Tables

Table 1. Optional Module Configurations............................................................................................. 27

Table 2. General Tolerance ................................................................................................................. 28

Table 3. Key Location/Pin Block Dimensions for Keys A - F ............................................................... 42

Table 4. Key Location/Pin Block Dimensions for Keys G - M .............................................................. 42

Table 5. RF Connector Physical Characteristics ................................................................................. 65

Table 6. RF Connector Mechanical Requirements .............................................................................. 65

Table 7. RF Connector Electrical Requirements ................................................................................. 66

Table 8. RF Connector Environmental Requirements ......................................................................... 66

Table 9. Recommended Antenna Function Allocation Table............................................................... 67

Table 10. Connector/Module Type Supported Matrix ............................................................................ 70

Table 11. Connector Physical Requirements......................................................................................... 71

Table 12. Connector Environmental Requirements ............................................................................... 72

Table 13. Connector Electrical Requirements ....................................................................................... 72

Table 14. Stand-off Height Descriptor Table.......................................................................................... 94

Table 15. Socket 1 System Interface Signals and Voltage Table ........................................................ 102

Table 16. Power-up CLKREQ# Timings .............................................................................................. 109

Table 17. Power-up Timing Variables .................................................................................................. 111

Table 18. DP_MLDIR Pin Termination ................................................................................................. 113

Table 19. SDIO Reset and Power-up Timing....................................................................................... 114

Table 20. Simple Indicator Protocol for LED States ............................................................................ 120

Table 21. Radio Operational States ..................................................................................................... 121

Table 22. SDIO Based Module Solution Pinouts (Module Key E) ....................................................... 123

Table 23. Display Port Based Module Solution Pinouts (Module Key A) ............................................ 124

Table 24. Socket 1 Module Pinouts (Module Key A-E) ........................................................................ 125

Table 25. Socket 2 System Interface Signal Table .............................................................................. 129

Table 26. GPIO Pin Function Assignment per Port Configuration ....................................................... 138

Table 27. Audio Pin Mode and Function Assignment .......................................................................... 140

Table 28. Antenna Control Pin Mode and Function Assignment ......................................................... 141

Table 29. Socket 2 Module Configuration ............................................................................................ 143

Table 30. Socket 2 Key B SSIC-based WWAN Module Pinouts ......................................................... 145

Table 31. Socket 2 Key B USB3.0-based WWAN Module Pinout ....................................................... 146

Table 32. Socket 2 Key B PCIe-based WWAN Module Pinout ........................................................... 147

Table 33. Socket 2 Key B-M SATA-based SSD Module Pinout .......................................................... 148

Table 34. Socket 2 Key B-M PCIe-based SSD Module Pinout............................................................ 149

Table 35. Socket 2 Key C WWAN Module Pinout ............................................................................... 150

PCI Express M.2 Specification

PCI Express M.2 Specification | 17

Revision 1.1, March 7, 2016

Table 36. Socket 3 System Interface Signal Table .............................................................................. 151

Table 37. Socket 3 SATA-based Module Pinouts (Module Key M) ..................................................... 154

Table 38. Socket 3 PCIe-based Module Pinouts (Module Key M)....................................................... 155

Table 39. BGA SSD System Interface Signal Table ............................................................................ 156

Table 40. DC Specification for 3.3 V Logic Signaling .......................................................................... 163

Table 41. DC Specification for 1.8 V Logic Signaling .......................................................................... 164

Table 42. Power Ramp Timing ............................................................................................................ 166

Table 43. Power Rail Slew Rate .......................................................................................................... 167

Table 44. Key Regulated Power Rail Parameters ............................................................................... 168

Table 45. Key VBAT Power Rail Parameters ...................................................................................... 168

Table 46. Power Rating Table for M.2 Modules with Connectors........................................................ 169

Table 47. Mechanical Key Assignments .............................................................................................. 171

Table 48. Socket 1 Versions ................................................................................................................ 172

Table 49. Display Port Based Socket 1 Pinout Diagram (Mechanical Key A) On Platform ................ 174

Table 50. SDIO Based Socket 1 Pinout Diagram (Mechanical Key E) On Platform ........................... 176

Table 51. Socket 2 Module Configuration Table .................................................................................. 178

Table 52. Socket 2 Pinouts Diagram (Mechanical Key B) On Platform ............................................... 180

Table 53. Socket 2 Pinout Diagram (Mechanical Key C) on Platform ................................................. 182

Table 54. Socket 3 SSD Pinout (Mechanical Key M) On Platform ...................................................... 183

Table 55. Signal Integrity Requirements and Test Procedures for M.2 ............................................... 193

Table 56. Example of Prepared Wire with Plug, Unit: mΩ ................................................................... 205

Table 57. Contact Resistance for the Sample Wires/Plugs, Unit: mΩ ................................................. 206

Table 58. Assumptions for Typical Components and Dissipation........................................................ 207

Table 59. Maximum Dissipation for WWAN Modules .......................................................................... 208

Table 60. Generic Assumptions for Package Designations and Types Expected to

Populate Modules ................................................................................................................ 208

Table 61. Assumptions for Generic System Environments ................................................................. 209

Table 62. Slot Definitions, Systems with Fans ..................................................................................... 210

Table 63. Slot Definitions, Systems without Fans ................................................................................ 210

Table 64. Example Use Case Applicable to Modules for Notebooks .................................................. 213

Table 65. Thermal Design Power Response – Notebook Category .................................................... 217

Table 66. Skin Temperature Limit Assumptions, Notebook ................................................................. 217

Table 67. Skin Temperature Effect of Module Position ....................................................................... 218

Table 68. Use Cases Applicable to Modules for Thin Platform Notebook with Fan ........................... 218

Table 69. Thermal Design Power Response – Thin Platform Notebook with Fan Category ............... 223

Table 70. Skin temperature limit assumptions, Thin platform notebook with Fan ............................... 223

Table 71. Use Cases Applicable to Modules for Tablet without Fan ................................................... 224

Table 72. Thermal Design Power Response—Tablet Category .......................................................... 227

Table 73. Skin Temperature Limit Assumptions, Tablet without Fan .................................................. 228

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