5
Introduction
Digital signal processors (DSPs) are used in a variety of applications to analyze real-time data or speed computationally intensive
tasks. A DSP is a microprocessor tuned to the task of number crunching by an instruction set that conveniently ties together special
hardware components needed for fast floating-point and fixed-point math and by powerful input/output (I/O) functions that keep
data flowing quickly. Design of the I/O for a digital-signal-processing system is one of the major factors that dictates the
machine’s performance. First-in, first-out (FIFO) memories often are used as data rate buffers to optimize the throughput of
digital-signal-processing systems and increase overall performance.
A FIFO is a dual-port memory with built-in write and read addressing to pass out data in the same order it is written. Data reads
and writes can be done asynchronous to one another. Flag circuitry indicates when the queue is empty or full, preventing
simultaneous read/write access to the same memory location. Advanced FIFO memories from Texas Instruments (TI) produced
in CMOS or BiCMOS technology also have user-programmable almost-empty and almost-full flags to measure the number of
words in memory. FIFOs provide a seamless bridge between two buses operating at different clock speeds and acting as temporary
data bins to exchange information between two systems without handshaking delay.
TI’s TMS320C3x and TMS320C4x processors are popular DSPs that include a 40-/32-bit floating-/fixed-point math unit, one
or two 32-bit external buses, and an on-board direct-memory-access (DMA) controller. Unidirectional and bidirectional clocked
FIFO devices from TI frequently are used to support systems built around these processors. Attractive features offered by TI
clocked FIFOs are synchronous (clocked) interface on each port, asynchronous I/O capability, programmable flags, maximum
write/read frequencies up to 80 MHz, maximum read access times as low as 9 ns, and fine-pitch surface-mount packaging.
DSP Applications Using FIFOs
DSP systems doing real-time data analysis or control functions use analog-to-digital (A/D) converters to translate
continuous-time, real-valued signals into discrete-time, integer-valued sequences. The rate used to sample the analog signal is
chosen based on the frequency bandwidth of the signal. This sample rate is independent of the microprocessor-bus rate, and
asynchronous buffering is required to pass the information to the DSP. Serial ports on the TMS320C3x/C4x processors provide
an asynchronous interface with A/D converters and are adequate when the incoming data traffic has a relatively low bit rate. For
higher bit rates, unidirectional clocked FIFOs provide a parallel buffer between the converters and the DSP bus.
Figure 1 shows several digitized signals, each using a FIFO for rate buffering to the processor bus. An example of this application
is multiplexing several analog telephone lines for compression or symbol detection. An input signal packet is gathered in the FIFO
and burst into memory by the DMA unit on the TMS320C3x/C4x. This method also is useful when the analog data is sampled
at a high rate for short duration, as in some medical-imaging equipment. Each FIFO holds its A/D samples in queue until the
processor retrieves the information that must be completed before the next sampling period. The block labeled FIFO Enable can
have a single-memory-space address and control the FIFOs in round-robin fashion as the DMA fills the random-access memory
(RAM) with digitized signals.