三星NOR MCP K5N5629ATB-BQ12技术规格书

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"SAMSUNG NOR MCP ADMUX 256_128_ K5N5629ATB_56Ball_8.00x9.20x1.20mm_1 0v.pdf" 这篇文档是关于三星（SAMSUNG）的一款非易失性存储器多芯片封装（MCP）产品——K5N5629ATB-BQ12的详细规格说明。"Nor"标签表明这是与NOR闪存相关的技术内容。该器件采用56球栅格阵列（Ball Grid Array, BGA）封装，尺寸为8.00mm x 9.20mm x 1.20mm，并工作在1.0V的电压环境下。 K5N5629ATB-BQ12是一款高密度的NOR闪存芯片，用于存储和快速访问代码。NOR闪存以其可以直接执行存储在其上的代码的能力而著名，常用于系统引导、嵌入式系统和微控制器等应用。256_128的描述可能表示该芯片具有256Mbit或32MB的存储容量，其中128可能是每个存储单元的位数，即128位并行接口。文档的开头部分声明，三星保留更改产品的权利，且提供的所有信息和规格可能会随时变更，而不另行通知。这意味着用户在设计中使用这款产品时应关注最新的数据手册和修订版。此外，三星明确指出，文档中的所有信息都是按“原样”提供，不提供任何明示或暗示的保证。文档还强调，三星的产品不适用于生命维持、重症监护、医疗、安全设备或类似应用，因为在这些应用中，产品故障可能导致生命或个人伤害。同样，三星的产品也不适用于军事或国防应用，以及可能有特殊条款或规定的政府采购项目。对于三星产品的更新或更多信息，用户应联系最近的三星办事处。最后，文档提到所有品牌名称、商标和注册商标均归其各自所有者所有，这表明三星尊重并遵守知识产权法规。这份文档提供了三星K5N5629ATB-BQ12 NOR闪存芯片的关键技术参数、使用限制和知识产权声明，是工程师在设计包含此组件的系统时的重要参考资料。

- 16 -

K5N5629ATB-BQ12 datasheet MCP Memory

Rev. 1.0

NOTE :

1) RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A23 ~ A14), DA : Bank Address (A23 ~ A20)

ABP : Address of the block to be protected or unprotected , DI :Die revision ID, CR : Configuration Register Setting,

WBL : Write Buffer Location, WC : Word Count

2) The 4th cycle data of autoselect mode and RD are output data. The others are input data.

3) Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WC and Device ID.

4) Unless otherwise noted, address bits A23–A11 are don’t cares.

5) The reset command is required to return to read mode.

If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode.

If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode.

If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that

bank was in erase suspend mode.

6) The 3rd and 4th cycle bank address of autoselect mode must be same.

Device ID Data : Top(2208H), Bottom(2209H), Uniform(3018H)

7) Normal Block Protection Verify : 00H for an unprotected block and 01H for a protected block.

OTP Block Protect verify (with OTP Block Address after Entering OTP Block) : 00H for unlocked, and 01H for locked.

8) 0H for handshaking, 1H for non-handshaking

9) The unlock bypass command sequence is required prior to this command sequence.

10) The system may read and program in non-erasing blocks when in the erase suspend mode.

The system may enter the autoselect mode when in the erase suspend mode.

The erase suspend command is valid only during a block erase operation, and requires the bank address.

11) The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address.

12) This mode is used only to enable Data Read by suspending the Program operation.

13) Set ABP(Address of the block to be protected or unprotected) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH

and A0 = VIL for protected.

14) Command is valid when the device is in Read mode or Autoselect mode.

15) For Buffer Program, Firstly Enter "Write to Buffer" Command sequence and then Enter Block Address and Word Count which is the number of word

data will be programmed. Word Count is smaller than the number of data wanted to program by one, Example if 15 words are wanted to program

then WC (Word Count) is 14. After Entering Command, Enter PA/PD’s (Program Addresses/ Program Data). Finally Enter "Program buffer to Flash"

Command sequence, This starts a buffer program operation. This Device supports 32-word Buffer Program.

There is some caution points.

- The number of PA/PD’s which are entered must be same to WC+1

- PA’s which are entered must be same A23~A5 address bits because Buffer Address is A23~A5 address and decided by PA entered firstly.

- If PA which are entered isn’t same Buffer Address, then PA/PD which is entered may be ignored and this buffer programming operation is aborted.

To return to normal operation, hardware reset or "Write to Buffer Abort Reset" command is issued.

- Overwrite for program buffer is also prohibited.

16) Command sequence resets device for next command after aborted write-to-buffer operation.

17) See "Set Burst Mode Configuration Register" for details.

18) On the third cycle, the data should be "C0h", address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be latched.

19) After software reset and write to buffer abort reset command, min. 5us recovery time is needed for normal read mode.

Command Definitions Cycle 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle

Write to Buffer

15)

Add

555H 2AAH BA BA PA WBL

Data AAH 55H 25H WC PD PD

Program buffer to Flash

15)

Add

Data 29H

Write to Buffer Abort Reset

16),19)

Add

555H 2AAH XXX

Data AAH 55H F0H

Set Burst Mode Configuration Register

17),18)

Add

555H 2AAH NOTE 18

Data AAH 55H C0H

Enter OTP Block Region

Add

555H 2AAH XXX

Data AAH 55H 70H

Exit OTP Block Region

Add

555H 2AAH 555H XXX

Data AAH 55H 75H 00H

- 17 -

K5N5629ATB-BQ12 datasheet MCP Memory

Rev. 1.0

4.0 DEVICE OPERATION

The device has inputs/outputs that accept both address and data information. To write a command or command sequence (which includes programming

data to the device and erasing blocks of memory), the system must drive CLK, AVD

and CE to VIL and OE to VIH when providing an address to the device,

and drive CLK, WE

and CE to VIL and OE to VIH when writing commands or data.

The device provides the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is

comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the

entire device can be erased. Table 16 indicates the address space that each block occupies. The device’s address space is divided into sixteen banks. A

“bank address” is the address bits required to uniquely select a bank. Similarly, a “block address” is the address bits required to uniquely select a block.

CC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specifi-

cation tables and timing diagrams for write operations.

4.1 Read Mode

The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode.

After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read(or

erase-suspend-read)mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode.

Sync MRS option

The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Burst Mode Configuration

4.1.1 Asynchronous Read Mode

For the asynchronous read mode a valid address should be asserted on A/DQ0-A/DQ15 and A16-A23, while driving CLK and AVD and CE to VIL. WE and

should remain at VIH. Note that CLK must remain low for asynchronous read mode. The address is latched at the rising edge of AVD, and then the

system can drive OE

to VIL. The data will appear on A/DQ0-A/DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled

for read access until the command register contents are altered.

Address access time (t

AA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling

edge of CE

to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. The asyn-

chronous access time is measured from a valid address, falling edge of AVD

or falling edge of CE whichever occurs last. To prevent the memory content

from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset.

4.1.2 Synchronous (Burst) Read Mode

The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should

determine how many clock cycles are desired for the initial word(t

IAA) of each burst access and what mode of burst operation is desired using

"Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be

read by synchronous read mode with a bank address which is programming or erasing. This status data by synchronous read mode can be

output and sustained until the system asserts CE

high or RESET low or AVD low in conjunction with a new address. To initiate the synchro

nous read again, a new address and AVD

pulse is needed after the host has completed status reads or the device has completed the pro

gram or erase operation.

4.1.3 Continuous Linear Burst Read

108/133Mhz with the Sync MRS option

The synchronous(burst) mode will automatically start on the rising edge of the CLK input while AVD is held low after Burst Mode Configuration

The initial word is output t

IAA after the rising edge of the last CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock

cycle, which automatically increments the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When

the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of additional

clock cycle can vary from zero to thirteen cycles, and the exact number of additional clock cycle depends on not olny the starting address of burst read but

also programmable wait state setting. The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential

burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the system asserts CE

high or RESET

low or AVD

low in conjunction with a new address.(See Table 7.) The reset command does not terminate the burst read operation. When it accesses the

bank is programming or erasing, continuous burst read mode will output status data. And status data will be sustained until the system asserts CE

high or

RESET

low or AVD low in conjunction with a new address. Note that at least 10ns is needed to start next burst read operation from terminating pre-

vious burst read operation in the case of asserting CE

high.

- 18 -

K5N5629ATB-BQ12 datasheet MCP Memory

Rev. 1.0

8-, 16-Word Linear Burst Read

As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap mode, in which a fixed number of words are read from consecutive

addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized

according to the number of words read in a single burst sequence for a given mode.(See Table. 9)

[Table 8] Burst Address Groups(Wrap mode only)

As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst

sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the

selected group. In a similar manner, 16-word wrap mode begins its burst sequence on the starting address written to the device, and then wrap back to

the first address in the selected address group.

4.2 Programmable Wait State

The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven from low to high for

burst read mode. Upon power up, the number of total initial access cycles defaults to fourteen.

4.3 Handshaking

The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready

to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode

Configuration Register" for details.) The rising edge of RDY after OE

goes low indicates the initial word of valid burst data. (RDY can be low active by

Extended configuration register A11 settng : RDY low indicates data valid) Using the autoselect command sequence, the handshaking feature will be ver-

ified in the device.

4.4 Set Burst Mode Configuration Register

The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode

configuration register must be set before the device enters burst mode. The burst mode configuration register is loaded with a three-cycle command

sequences. On the third cycle, the data should be C0h, address bits A10-A0 should be 101_0101_0101b, and address bits A21-A11 set the code to be

latched. The device returns to default setting after power up or hardware reset.

4.4.1 Programmable Wait State Configuration

This feature informs the device the number of clock cycles that must elapse after AVD is driven from low to high before data will be available. This value

is determined by the input frequency of the device. Address bits A14-A11 determine the setting. (See Configuration Register table 10.) The Programma-

ble wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will revert

the wait state to the default setting, that is 14 initial cycles.

4.4.2 Burst Read Mode Setting

The device supports three different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap.

4.4.3 RDY Configuration

By default, the RDY pin will be high whenever there is valid data on the output. (RDY can be low active by Extended configuration register A11 settng :

RDY low indicates data valid) The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting.

The RDY pin behaves same way in word boundary crossing case.

[Table 9] Burst Mode Configuration Register Table

Burst Mode Group Size Group Address Ranges

8 word 8 words 0-7h, 8-Fh, 10-17h, ....

16 word 16 words 0-Fh, 10-1Fh, 20-2Fh, ....

Address Bit Function Settings(Binary)

A19 Read Mode

1 = Synchronous Burst Read Mode

0 = Asynchronous Read Mode (default)

A18 RDY Active

1 = RDY active one clock cycle before data

0 = RDY active with data(default)

- 19 -

K5N5629ATB-BQ12 datasheet MCP Memory

Rev. 1.0

NOTE :

Initial wait state should be set according to it’s clock frequency. Table 10 recommend the program wait state for each clock frequencies.

Not 100% tested

[Table 10] Burst Address Sequences

4.5 Autoselect Mode

By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read

mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Standard asynchronous read

cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition,

this mode allows the host system to verify the block protection or unprotection. Table 13 shows the address and data requirements. The autoselect com-

mand sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The

autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated

by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block

address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiat-

ing another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write

Reset command(F0H) into the command register.

[Table 11] Autoselect Mode Description

4.6 Standby Mode

When the CE inputs is held at VCC ± 0.2V, and the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption.

In this mode, the device outputs are placed in the high impedence state, independent of the OE

input. When the device is in either of these standby

modes, the device requires standard access time (tCE) for read access before it is ready to read data. If the device is deselected during erasure or pro-

gramming, the device draws active current until the operation is completed. I

CC5 in the DC Characteristics table represents the standby current specifica-

tion.

4.7 Automatic Sleep Mode

The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses

A17

Burst Read Mode

000 = Continuous(default)

001 = 8-word linear with wrap

010 = 16-word linear with wrap

011~111 = Reserve

A16

A15

A14

Programmable Wait State

0000 = Data is valid on the 4th active CLK edge after AVD

transition to VIH

0001 = Data is valid on the 5th active CLK edge after AVD

transition to VIH (40Mhz*)

0010 = Data is valid on the 6th active CLK edge after AVD

transition to VIH (50/54Mhz*)

0011 = Data is valid on the 7th active CLK edge after AVD

transition to VIH (60/66Mhz*)

0100 = Data is valid on the 8th active CLK edge after AVD

transition to VIH (70Mhz*)

0101 = Data is valid on the 9th active CLK edge after AVD

transition to VIH (80/83Mhz*)

0110 = Data is valid on the 10th active CLK edge after AVD

transition to VIH (90/100Mhz*)

0111 = Data is valid on the 11th active CLK edge after AVD

transition to VIH (108/110Mhz*)

1000 = Data is valid on the 12th active CLK edge after AVD

transition to VIH (120Mhz*)

1001 = Data is valid on the 13th active CLK edge after AVD

transition to VIH (133Mhz*,default)

1010 = Data is valid on the 14th active CLK edge after AVD

transition to VIH

1011 = Data is valid on the 15th active CLK edge after AVD

transition to VIH

A13

A12

A11

Start

Addr.

Burst Address Sequence

Continuous Burst 8-word Burst 16-word Burst

Wrap

0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -D-E-F

1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-0 1-2-3-4 ... -E-F-0

2 2-3-4-5-6-7-8... 2-3-4-5-6-7-0-1 2-3-4-5 ... -F-0-1

Description Address Read Data

Manufacturer ID (DA) + 00H ECH

Device ID (DA) + 01H

Top boot(2208H), Bottom boot(2209H), Uniform block(3018H)

Block Protection/Unprotection (BA) + 02H 01H (protected), 00H (unprotected)

Handshaking (DA) + 03H 0H : handshaking, 1H : non-handshaking

- 20 -

K5N5629ATB-BQ12 datasheet MCP Memory

Rev. 1.0

remain stable for tAA+60ns, the device automatically enables this mode. The Automatic sleep mode is depends on the CE, WE and OE signal, so CE, WE

and OE

signals are held at any state. In a sleep mode, output data is latched and always available to the system. When OE is active, the device provides

new data without wait time. Automatic sleep mode current is equal to standby mode current.

4.8 Output Disable Mode

When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state.

4.9 Block Protection & Unprotection

To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are pro-

tected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are

don’t care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0

whether that block should be protected (A6 = V

IL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can

continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command).

The device offers three types of data protection at the block level :

• The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block.

• When WP

is at VIL, the two outermost blocks are protected.(Boot block part)

• When WP

is at VIL, the last one block (BA255) is protected.(Uniform block part)

• When V

PP is at VIL, all blocks are protected.

Note that user never float the V

pp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL.

4.10 Hardware Reset

The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the

device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET

pulse.

The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated

once the device is ready to accept another command sequence. The RESET

pin may be tied to the system reset pin. If a system reset occurs during the

Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode;

this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET

is asserted during a program or erase opera-

tion, the device requires a time of tREADY (during Internal Routines) before the device is ready to read data again. If RESET

is asserted when a program

or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data

after RESET

returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 12 for the timing diagram. When RESET is at

logic high, the device is in standard operation.

4.11 Software Reset

The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in

Don’t Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in an pro-

gram command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is

completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode. The reset command valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the

reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset

command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing

the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset com-

mand returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend)

4.12 Program

The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order

to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned

for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The

device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution

of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will

be ignored.

4.13 Accelerated Program

The device provides accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible.

When V

ID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unpro-

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