PGA5807A
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ZHCSBT8 –OCTOBER 2013
Table 1. PIN FUNCTIONS
NAME NO. FUNCTION DESCRIPTION
17, 28, 31, 49,
AVDD Supply Analog supply pin, 3.3 V
62-64
19, 20, 24, 27,
AVSS Ground Analog ground
29, 50, 54, 61
When RESET is high, this pin is used to program the PGA gain.
GAIN0 51 Digital input
Refer to Table 2 for more details. Note: Use 3.3-V logic.
When RESET is high, this pin is used to program the PGA gain.
GAIN1 52 Digital input
Refer to Table 2 for more details. Note: Use 3.3-V logic.
When RESET is high, this pin is used to program the PGA gain.
GAIN2 56 Digital input
Refer to Table 2 for more details. Note: Use 3.3-V logic.
INM1 2 Input Complimentary analog input for channel 1
INP1 1 Input Analog input for channel 1
INM2 4 Input Complimentary analog input for channel 2
INP2 3 Input Analog input for channel 2
INM3 6 Input Complimentary analog input for channel 3
INP3 5 Input Analog input for channel 3
INM4 8 Input Complimentary analog input for channel 4
INP4 7 Input Analog input for channel 4
The dc input common-mode can be 2.1 V ± 200 mV.
INM5 10 Input Complimentary analog input for channel 5
INP5 9 Input Analog input for channel 5
INM6 12 Input Complimentary analog input for channel 6
INP6 11 Input Analog input for channel 6
INM7 14 Input Complimentary analog input for channel 7
INP7 13 Input Analog input for channel 7
INM8 16 Input Complimentary analog input for channel 8
INP8 15 Input Analog input for channel 8
21-23, 25, 26,
NC — Unused pins; do not connect
30, 32
OUTM1 47 Output Complimentary output pin for channel 1
OUTP1 48 Output Output pin for channel 1
OUTM2 45 Output Complimentary output pin for channel 2
OUTP2 46 Output Output pin for channel 2
OUTM3 43 Output Complimentary output pin for channel 3
OUTP3 44 Output Output pin for channel 3
OUTM4 41 Output Complimentary output pin for channel 4
OUTP4 42 Output Output pin for channel 4
The common-mode voltage is 0.95 V.
OUTM5 39 Output Complimentary output pin for channel 5
OUTP5 40 Output Output pin for channel 5
OUTM6 37 Output Complimentary output pin for channel 6
OUTP6 38 Output Output pin for channel 6
OUTM7 35 Output Complimentary output pin for channel 7
OUTP7 36 Output Output pin for channel 7
OUTM8 33 Output Complimentary output pin for channel 8
OUTP8 34 Output Output pin for channel 8
Partial power-down control pin for the entire device with an internal 20-kΩ pull-down resistor; active high.
PDN 53 Digital input
Note: Use 3.3-V logic.
RESET 60 Digital input Logic hardware reset pin. Note: Use 3.3-V logic.
SCLK 59 Digital input Serial interface clock pin with an internal 20-kΩ pull-down resistor. Note: Use 3.3-V logic.
Serial interface data input with an internal 20-kΩ pull-down resistor. When RESET is high, the corner
SDATA 58 Digital input frequency for the antialias filter can be programmed to a lower frequency (60 MHz) by setting this pin high.
Note: Use 3.3-V logic.
SDOUT 55 Digital output Serial interface readout pin
Serial interface enabled for channels 1 to 8 with an internal 20-kΩ pull-up resistor; active low.
SEN 57 Digital input
Note: Use 3.3-V logic.
VBIAS 18 Decap Bias voltage; bypass to ground with a 1-μF capacitor or greater
Copyright © 2013, Texas Instruments Incorporated 5
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