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JEDEC Standard No. 84-A441
-xii-
Embedded MultiMediaCard(e•MMC) e•MMC/Card Product Standard, High Capacity,
including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports,
Security Enhancement, Background Operation and High Priority Interrupt (MMCA, 4.41)
CONTENTS(continued)
Page
Figure 43 — Stop transmission after last data block; card is busy programming ................................ 107
Figure 44 — Stop transmission after last data block; card becomes busy............................................ 107
Figure 45 — Bus test procedure timing ................................................................................................ 108
Figure 46 — Boot operation, termination between consecutive data blocks........................................ 108
Figure 47 — Boot operation, termination during transfer .................................................................... 109
Figure 48 — Bus mode change timing (push-pull to open-drain) ........................................................ 109
Figure 49 — Alternative boot operation, termination between consecutive data blocks...................... 110
Figure 50 — Alternative boot operation, termination during transfer .................................................. 110
Figure 51 — H/W reset waveform........................................................................................................ 112
Figure 52 — Noise filtering timing for H/W reset................................................................................ 112
Figure 53 — CRC7 generator/checker.................................................................................................. 158
Figure 54 — CRC16 generator/checker................................................................................................ 159
Figure 55 — Bus circuitry diagram....................................................................................................... 163
Figure 56 — Improper power supply.................................................................................................... 164
Figure 57 — Shortcut protection........................................................................................................... 164
Figure 58 — Power-up diagram............................................................................................................ 165
Figure 59 — e•MMC power-up diagram ..............................................................................................167
Figure 60 — The e•MMC power cycle................................................................................................. 168
Figure 61 — MultiMediaCard bus driver ............................................................................................. 170
Figure 62 — e•MMC internal power diagram ...................................................................................... 172
Figure 63 — Bus signal levels .............................................................................................................. 174
Figure 64 — Timing diagram: data input/output .................................................................................. 176
Figure 65 — Timing diagram: data input/output in dual data rate mode.............................................. 179
Figure A.1 — Power supply decoupling................................................................................................. 185
Figure A.2 — Modified MultiMediaCard connector for hot insertion ................................................... 186
Figure A.3 — Legend for command-sequence flow charts .................................................................... 189
Figure A.4 — SEND_OP_COND command flow chart ........................................................................ 190
Figure A.5 — CIM_SINGLE_CARD_ACQ .......................................................................................... 191
Figure A.6 — CIM_SETUP_CARD....................................................................................................... 192
Figure A.7 — CIM_STREAM_READ................................................................................................... 193
Figure A.8 — CIM_READ_BLOCK ..................................................................................................... 193
Figure A.9 — CIM_READ_MBLOCK.................................................................................................. 194
Figure A.10 — CIM_WRITE_MBLOCK ................................................................................................ 195
Figure A.11 — CIM_ERASE_GROUP.................................................................................................... 196
Figure A.12 — CIM_SECURE_ERASE..................................................................................................197
Figure A.13 — CIM_SECURE_TRIM..................................................................................................... 198
Figure A.14 — CIM_TRIM...................................................................................................................... 199
Figure A.15 — CIM_US_PWR_WP ........................................................................................................ 200
Figure A.16 — CIM_US_PERM_WP...................................................................................................... 201
Figure A.17 — Bus testing for eight data lines......................................................................................... 205
Figure A.18 — Bus testing for four data lines .......................................................................................... 205
Figure A.19 — Bus testing for one data line ............................................................................................ 205
Figure A.20 — Erase-unit size selection flow .......................................................................................... 207
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