Version 1.0 Specification for A-PHY
06-Aug-2020
ix
Copyright © 202
0 MIPI Alliance, Inc.
All rights reserved.
Figures
Figure 1 Data and Power Logical Structure ..................................................................................... 8
Figure 2 High Level Layer Structure ................................................................................................ 8
Figure 3 A-PHY High Level Structure ........................................................................................... 11
Figure 4 A-PHY Interconnect ......................................................................................................... 15
Figure 5 Cable Topologies .............................................................................................................. 16
Figure 6 Set-up for S-parameter Characterization of End Nodes and TLIS ................................... 17
Figure 7 Interconnect Test Points Definition .................................................................................. 18
Figure 8 Coax and SDP Cable Insertion Loss Limits ..................................................................... 19
Figure 9 Cable TLIS Return Loss Limits ....................................................................................... 20
Figure 10 Cable TLIS Coupling Attenuation ................................................................................. 21
Figure 11 Cable TLIS Attenuation Limits ...................................................................................... 22
Figure 12 Alien Cable Bundle Crosstalk Limit .............................................................................. 23
Figure 13 Single-Ended End Node Routing Example .................................................................... 24
Figure 14 End Node Insertion Loss Limit ...................................................................................... 25
Figure 15 End Node Return Loss Limits ........................................................................................ 26
Figure 16 Receiver ANEXT Limit ................................................................................................. 27
Figure 17 PCB-Based Interconnect ................................................................................................ 28
Figure 18 Power Ripple Gain Function .......................................................................................... 29
Figure 19 Power Over Coax (PoC) Configuration ......................................................................... 30
Figure 20 Power Over Differential Line (PoDL) Configuration .................................................... 30
Figure 21 Examples of Applicable Pulses ...................................................................................... 32
Figure 22 P2 Decaying Sawtooth Model at 40 MHz / 4 nS Tr / 150 mV to 15 mV in 150 nS....... 33
Figure 23 Alien Bundle PSD Limit Line ........................................................................................ 34
Figure 24 A-PHY Unified Architecture .......................................................................................... 35
Figure 25 A-PHY P1 G1/G2 Architecture ...................................................................................... 37
Figure 26 A-PHY P2 G1/G2 Architecture ...................................................................................... 38
Figure 27 A-PHY P2 G4/G5 Architecture ...................................................................................... 39
Figure 28 Dynamically Modulated, Time Bounded, Local Retransmission .................................. 41
Figure 29 TX RTS Over 8B/10B PCS Block Diagram .................................................................. 42
Figure 30 TX RTS Over PAM-X PCS Block Diagram .................................................................. 43
Figure 31 Single Retransmission Request Sent Over Downlink .................................................... 50
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