NAU8401
Datasheet Rev 2.0 Page 12 of 69 January 25, 2011
2 Power Supply
This device has been designed to operate reliably using a wide range of power supply conditions and power-
on/power-off sequences. There are no special requirements for the sequence or rate at which the various power
supply pins change. Any supply can rise or fall at any time without harm to the device. However, pops and clicks
may result from some sequences. Optimum handling of hardware and software power-on and power-off sequencing
is described in more detail in the Applications section of this document.
2.1.1 Power-On Reset
The NAU8401 does not have an external reset pin. The device reset function is automatically generated internally
when power supplies are too low for reliable operation. The internal reset is generated any time that either VDDA
or VDDC is lower than is required for reliable maintenance of internal logic conditions. The reset threshold voltage
for VDDA and VDDC is approximately 0.5Vdc. If both VDDA and VDDC are being reduced at the same time, the
threshold voltage may be slightly lower. Note that these are much lower voltages than are required for normal
operation of the chip. These values are mentioned here as general guidance as to overall system design.
If either VDDA or VDDC is below its respective threshold voltage, an internal reset condition is asserted. During
this time, all registers and controls are set to the hardware determined initial conditions. Software access during this
time will be ignored, and any expected actions from software activity will be invalid.
When both VDDA and VDDC reach a value above their respective thresholds, an internal reset pulse is generated
which extends the reset condition for an additional time. The duration of this extended reset time is approximately
50 microseconds, but not longer than 100 microseconds. The reset condition remains asserted during this time. If
either VDDA or VDDC at any time becomes lower than its respective threshold voltage, a new reset condition will
result. The reset condition will continue until both VDDA and VDDC again higher than their respective thresholds.
After VDDA and VDDC are again both greater than their respective threshold voltage, a new reset pulse will be
generated, which again will extend the reset condition for not longer than an additional 100 microseconds.
2.1.2 Power Related Software Considerations
There is no direct way for software to determine that the device is actively held in a reset condition. If there is a
possibility that software could be accessing the device sooner than 100 microseconds after the VDDA and VDDC
supplies are valid, the reset condition can be determined indirectly. This is accomplished by writing a value to any
register other than register 0x00, with that value being different than the power-on reset initial values. The optimum
choice of register for this purpose may be dependent on the system design, and it is recommended the system
engineer choose the register and register test bit for this purpose. After writing the value, software will then read
back the same register. When the register test bit reads back as the new value, instead of the power-on reset initial
value, software can reliably determine that the reset condition has ended.
Although it is not required, it is strongly recommended that a Software Reset command should be issued after
power-on and after the power-on reset condition is ended. This will help insure reliable operation under every
power sequencing condition that could occur.
If there is any possibility that VDDA or VDDC could be unreliable during system operation, software may be
designed to monitor whether a power-on reset condition has happened. This can be accomplished by writing a test
bit to a register that is different from the power-on initial conditions. This test bit should be a bit that is never used
for any other reason, and does not affect desired operation in any way. Then, software at any time can read this bit
to determine if a power-on reset condition has occurred. If this bit ever reads back other than the test value, then
software can reliably know that a power-on reset event has occurred. Software can subsequently re-initialize the
device and the system as required by the system design.
2.1.3 Software Reset
All chip registers can be reset to power-on default conditions by writing any value to register 0, using any of the
control modes. Writing valid data to any other register disables the reset, but all registers need to have the correct
operating data written. See the applications section on powering NAU8401 up for information on avoiding pops and
clicks after a software reset.