富士电机FRENIC-VG变频器操作与维护手册

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"富士变频器FRENIC-VG系列的使用说明书,涵盖了该高性能矢量控制型变频器的参数设置和安全注意事项" 富士变频器FRENIC-VG系列是专为控制三相电动机变速运行设计的设备。用户在使用前必须详细阅读并理解使用说明书,以避免操作不当导致的设备故障或性能下降。变频器的正确使用对于设备的正常运转和寿命至关重要。说明书特别强调,应将手册交给实际操作的最终用户,并且手册需伴随设备直至报废。 说明书提醒用户,某些选配件的使用方法不在本手册中详细说明,需参考相应的选配件手册。此外,FRENIC-VG的主要功能在此手册中有记载,但更详尽的信息则可在用户手册中找到。富士电机株式会社保留对说明书的所有权,禁止未经授权的复制或转贴。 关于高次谐波抑制,手册提到了与高压或特高压用电设备相关的应用,用户可参阅《FRENIC-VG用户手册》的“附录”获取更多信息。手册的"安全注意事项"部分从安装环境、保管环境以及外围设备连接等方面提供了详细的指导。 在安装环境方面,用户需要注意合适的温度、湿度、尘埃等级以及振动情况,以确保变频器的稳定工作。在保管环境中,区分了暂时和长期保管的注意事项,包括防潮、防尘和防高温。 在与外围设备连接时,变频器不能与进相电容器直接连接,电源系统中可能需要直流或交流电抗器来改善输入功率因数。同时,推荐使用适当的断路器和电磁接触器进行保护,以及考虑浪涌吸收器和抑制器的安装以防止电压波动对设备的影响。 干扰对策部分,手册提到了如何减少电磁干扰,确保变频器和其他设备之间的兼容性。这些详细的信息旨在帮助用户实现安全、高效且可靠的变频器运行。

*** Using Compiler '', folder: 'E:\Keil_v5\ARM\ARMCLANG\Bin' Build target 'Target 1' compiling core_cm3.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\core_cm3.__i"' compiling system_stm32f10x.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\system_stm32f10x.__i"' compiling misc.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\misc.__i"' compiling stm32f10x_bkp.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\stm32f10x_bkp.__i"' compiling stm32f10x_adc.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\stm32f10x_adc.__i"' compiling stm32f10x_can.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\stm32f10x_can.__i"' compiling stm32f10x_cec.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\stm32f10x_cec.__i"' compiling stm32f10x_crc.c... *** Error: CreateProcess failed, Command: '"E:\Keil_v5\ARM\ARMCLANG\Bin\ArmCC" --via ".\objects\stm32f10x_crc.__i"' linking... .\Objects\test.axf: Error: L6967E: Entry point (0x08000000) points to a Thumb instruction but is not a valid Thumb code pointer. Finished: 0 information, 0 warning and 1 error messages. ".\Objects\test.axf" - 1 Error(s), 0 Warning(s). Target not created. Build Time Elapsed: 00:00:00

2023-07-14 上传

请逐行注释下面的代码:class riscv_instr_base_test extends uvm_test; riscv_instr_gen_config cfg; string test_opts; string asm_file_name = "riscv_asm_test"; riscv_asm_program_gen asm_gen; string instr_seq; int start_idx; uvm_coreservice_t coreservice; uvm_factory factory; uvm_component_utils(riscv_instr_base_test) function new(string name="", uvm_component parent=null); super.new(name, parent); void'($value$plusargs("asm_file_name=%0s", asm_file_name)); void'($value$plusargs("start_idx=%0d", start_idx)); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); coreservice = uvm_coreservice_t::get(); factory = coreservice.get_factory(); uvm_info(gfn, "Create configuration instance", UVM_LOW) cfg = riscv_instr_gen_config::type_id::create("cfg"); uvm_info(gfn, "Create configuration instance...done", UVM_LOW) uvm_config_db#(riscv_instr_gen_config)::set(null, "*", "instr_cfg", cfg); if(cfg.asm_test_suffix != "") asm_file_name = {asm_file_name, ".", cfg.asm_test_suffix}; // Override the default riscv instruction sequence if($value$plusargs("instr_seq=%0s", instr_seq)) begin factory.set_type_override_by_name("riscv_instr_sequence", instr_seq); end if (riscv_instr_pkg::support_debug_mode) begin factory.set_inst_override_by_name("riscv_asm_program_gen", "riscv_debug_rom_gen", {gfn, ".asm_gen.debug_rom"}); end endfunction function void report_phase(uvm_phase phase); uvm_report_server rs; int error_count; rs = uvm_report_server::get_server(); error_count = rs.get_severity_count(UVM_WARNING) + rs.get_severity_count(UVM_ERROR) + rs.get_severity_count(UVM_FATAL); if (error_count == 0) begin uvm_info("", "TEST PASSED", UVM_NONE); end else begin uvm_info("", "TEST FAILED", UVM_NONE); end uvm_info("", "TEST GENERATION DONE", UVM_NONE); super.report_phase(phase); endfunction virtual function void apply_directed_instr(); endfunction task run_phase(uvm_phase phase); int fd; for(int i = 0; i < cfg.num_of_tests; i++) begin string test_name; randomize_cfg(); riscv_instr::create_instr_list(cfg); riscv_csr_instr::create_csr_filter(cfg); asm_gen = riscv_asm_program_gen::type_id::create("asm_gen", , gfn); asm_gen.cfg = cfg; asm_gen.get_directed_instr_stream(); test_name = $sformatf("%0s_%0d.S", asm_file_name, i+start_idx); apply_directed_instr(); uvm_info(gfn, "All directed instruction is applied", UVM_LOW) asm_gen.gen_program(); asm_gen.gen_test_file(test_name); end endtask virtual function void randomize_cfg(); DV_CHECK_RANDOMIZE_FATAL(cfg); uvm_info(`gfn, $sformatf("riscv_instr_gen_config is randomized:\n%0s", cfg.sprint()), UVM_LOW) endfunction endclass

2023-05-24 上传