Copley DataSheet:高速轴控LSI驱动运动系统

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4-2. Terminal allocation diagram

Note: As you can see in the figure above, pin number 1 is to the lower left of the LSI model name marked on

the chip.

#BSY/PH1

#FUP/PH2

#FDW/PH3

#MVC/PH4

ELL

GND

#MSEL

#MRER

#TOUT

BRK

TUD

TMD

VDD

CLK

GND

CKSL

SPD0

SPD1

GND

#RST

INP

CLR

LTC

PCS

#CP3

#CP2

#CP1

VDD

DIR

OUT

ERC

GND

VDD

GND

VDD

#DN0

#DN1

#DN2

#DN3

#DN4

#DN5

VDD

GND

#DNSO

DNSM

SOEI

#SOEL

SOEH

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

JAPAN

XXXXXXXXX

G9003

XXXX

VDD

GND

#STP

#STA

VDD

ALM

ORG

-EL

+EL

#EMG

GND

- 12 -

4-4. Functions of terminals

4-4-1. CLK

This is an input terminal of the reference clock. By setting the CKSL terminal, either of the following clock

rate signals can be connected.

CKSL = L: 40 MHz

CKSL = H: 80 MHz

By selecting either of these clock rates, the serial communication transfer rate does not change. This

clock rate selection affects communication precision.

For a small-scale serial communication and transfer rate below 10 Mbps, use of the center device with 40

MHz does not give any restriction.

With 20 Mbps transfer speed; however, a longer communication line or a large number of connected local

devices may deteriorate communication precision due to collapse of signals on the circuit. This

deterioration of communication quality can be corrected inside the LSI if the deterioration level is not

much. In order to improve correction precision; however, evenness of the clock duty is required. In other

words, if the duty is ideal (50:50), the capacity to correct collapse of the signals in the communication lines

can be improved. On the contrary, if the duty is not ideal, the center device cannot cope with collapses of

the communication line.

As a result, if the duty is close to ideal, the center device can be used with 40 MHz. When connecting

more than one oscillator, the duty will not be ideal. In this case, select 80 MHz. The center device divides

the frequency inside and creates 40 MHz frequency.

If you do not want to use 80 MHz frequency, you may prepare a separate 40 MHz oscillator for this LSI.

The CLK terminal cannot be connected to 5 V. Supply only a 3.3 V CMOS level signal to the CLK terminal

4-4-2. #RST

This is an input terminal for a reset signal.

By input L level signal, the center device is reset. As the center device synchronizes with a clock, arrange

a circuit so that it does not disconnect the clock while resetting. Longer than 10 clock cycles is required

during resetting.

4-4-3. CKSL

Use to select clock rate.

L: Connect 40 MHz clock frequency to the CLK terminal.

H: Connect 80 MHz clock frequency to the CLK terminal.

Select this when the duty of the 40 MHz clock collapses a lot.

4-4-4. #DN0 to #DN5

Input terminals for setting device address.

Since these terminals use negative logic, setting all the terminals to LOW calls up device address "3Fh."

There are two methods for entering a device address. Select the input method using the DNSM terminal.

- 13 -

4-4-5. DNSM

Select the input method for loading the device address.

1) When the DNSM = H

Specify an address from 00h to 3Fh using the #DN0 to #DN5 terminals.

2) When the DNSM = L

Input a #DNSO signal that is output by some other chip on the #DN0 terminal on this device. When

using this input method, this chip has an address equal to the other chip's address plus one.

When using this method, connect terminals #DN1 to #DN5 to GND.

When two sequential sets of serial data match, the data is taken to be a device address.

4-4-6. #DNSO

The numeric equivalent of the address on #DN0 to #DN5 + 1 will be output after being converted into a

serial bit stream.

Connect this output to another local device's #DN0 terminal (make all the other DNSM terminals of that

local device LOW), so that other devices can get the address and pass it along to the next data-sending

device.

Please note that the next address after "3Fh" (#DN(5:0) = " 000000") is "00h."

In the case that continuous address by #DNSO signal is set, it is necessary to have at least approximately

50 µs until the next address is confirmed.

4-4-7. SPD0, SPD1

Set the communication speed

All of the devices on the same communication line must be set to the same speed.

SPD1 SPD0 Communication speed

L L 2.5 Mbps

L H 5 Mbps

H L 10 Mbps

H H 20 Mbps

4-4-8. TUD

A watchdog timer is included on the chip to assist in administration of the communication status (see the

"TMD" terminal section).

When the data transmission interval from a center device to this device exceeds the set time, the

watchdog timer times out.

This terminal is used to set output conditions when the watchdog timer times out.

When TUD = HIGH --- The LSI keeps its current status.

When the TUD = LOW --- Reset I/O port output, and immediately stops pulse output (stop operation).

4-4-9. TMD

Specify the time for the watchdog timer.

The watchdog timer is used to administer the communication status.

When the interval between data packets sent from a center device is longer than the specified interval, the

watchdog timer times out (the timer restarts its count at the end of each data packet received from a

center device). The time out may occur because of a problem on the communication circuit, such as

disconnection, or simply because the center device has stopped communicating.

The time used by the watchdog timer varies with communication speed selected.

TMD terminal

Watchdog timer setting

20 Mbps 10 Mbps 5 Mbps 2.5 Mbps

L 5 ms 10 ms 20 ms 40 ms

H 20 ms 40 ms 80 ms 160 ms

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