12Gbps HDMI 2.1混合转接驱动器TMDS1204：高性能、兼容与应用

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TI-TMDS1204是一款高性能的HDMI转接驱动器，专为满足新一代高清多媒体接口（HDMI）2.1标准设计。这款器件的最大亮点是其能够提供高达12Gbps的数据传输速率，这使得它在连接笔记本电脑、台式机、电视、家庭影院系统、游戏设备以及专业音频/视频和标牌等应用场景中表现出色。它支持HDMI1.4b和HDMI2.0b的向下兼容，特别适合于HDMI2.1的FRL（固定速率链路）模式，能够处理3、6、8、10和12Gbps的多种速率，包括三通道和四通道。 TMDS1204的优势在于它的高级特性，例如6GHz时的12dB自适应和固定均衡器，确保了信号传输的稳定性和清晰度。通过I2C或引脚搭接的方式，用户可以对其进行编程，以适应不同的应用需求。内置的HPD电平转换器允许与1.8V和3.3V的LVCMOS电平兼容，提高了灵活性。主通道支持全通道交换，便于在需要独立时钟和数据路径的系统中使用。为了优化HDMI接收器的性能，该驱动器还配备了信号检测输出指示器和数字显示控制（DDC）监控功能，能够实时监测链路状态并提供配置信息。在功耗方面，TMDS1204表现出极佳的节能特性，如在12GFRL四通道有源限制和线性工作模式下分别消耗575mW和220mW，而在断电状态下仅消耗0.6mW。这意味着在保持高性能的同时，能有效降低系统的能耗。封装方面，TMDS1204采用紧凑的40引脚0.4mm间距4mm×6mm WQFN封装，适合于小型化设计，且工作温度范围广泛，适应商业级和工业级环境。电源需求简单，只需要一个3.3V单电源即可运行。此外，TMDS1204还提供了简化版原理图，方便工程师理解和使用。 TMDS1204是一款高度集成且灵活的HDMI转接解决方案，能够提供高效、稳定、兼容的连接体验，是现代电子设备连接HDMI接口的理想选择。

6.5 Electrical Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TERM2+

Internal termination for DR > 3.4 Gbps

when DC-coupled.

TERM = 3h; AC_EN = L (DC-coupled);

HPD_IN=H; Active state; –20℃ ≤ T

≤

85℃;

85 100 115

TERM2+

Internal termination for DR > 3.4 Gbps

when AC-coupled.

TERM = 3h; AC_EN = H (AC-

coupled); HPD_IN=H; Active state; –

20℃ ≤ T

≤ 85℃;

85 100 115

TXPRE0-

RATIO

Transmitter FFE pre-emphasis ratio for 0

dB.

TERM = 3h; HPD_IN = H; TX_AC_EN =

0; CLK_TXFFE = 0h; CLK_VOD = 3h;

D0_TXFFE = 0h; D0_VOD = 3h;

D1_TXFFE = 0h; D1_VOD = 3h;

D2_TXFFE = 0h; D2_VOD = 3h; 20 * log

(Vp/Vn); 128 zeros followed by 128 ones;

0 dB

TXPRE1-

RATIO

Transmitter FFE pre-emphasis ratio for

3.5 dB for data lanes

At 5.94 Gbps HDMI 2.0; TERM = 3h;

HPD_IN = H; TX_AC_EN = 0;

CLK_TXFFE = 0h; CLK_VOD = 3h;

D0_TXFFE = 1h; D0_VOD = 3h;

D1_TXFFE = 1h; D1_VOD = 3h;

D2_TXFFE = 1h; D2_VOD = 3h; 20 * log

(Vp/Vn); 128 zeros followed by 128 ones;

4.0 dB

TXPRE2-

RATIO

Transmitter FFE pre-emphasis ratio for 6

dB for data lanes

At 5.94 Gbps HDMI 2.0; TERM = 3h;

HPD_IN = H; TX_AC_EN = 0;

CLK_TXFFE = 0h; CLK_VOD = 3h;

D0_TXFFE = 2h; D0_VOD = 3h;

D1_TXFFE = 2h; D1_VOD = 3h;

D2_TXFFE = 2h; D2_VOD = 3h; 20 * log

(Vp/Vn); 128 zeros followed by 128 ones;

6.5 dB

TXFFE0-

RATIO

Transmitter FRL TXFFE0 de-emphasis

ratio

At 12 Gbps FRL; TERM = 3h; HPD_IN =

H; TX_AC_EN = 0; CLK_TXFFE = 4h;

CLK_VOD = 3h; D0_TXFFE = 4h;

D0_VOD = 3h; D1_TXFFE = 4h; D1_VOD

= 3h; D2_TXFFE = 4h; D2_VOD = 3h; 20

* log (Vp/Vn); 128 zeros followed by 128

ones;

-2.5 dB

TXFFE1-

RATIO

Transmitter FRL TXFFE1 de-emphasis

ratio

At 12 Gbps FRL; TERM = 3h; HPD_IN =

H; TX_AC_EN = 0; CLK_TXFFE = 5h;

CLK_VOD = 3h; D0_TXFFE = 5h;

D0_VOD = 3h; D1_TXFFE = 5h; D1_VOD

= 3h; D2_TXFFE = 5h; D2_VOD = 3h; 20

* log (Vp/Vn); 128 zeros followed by 128

ones;

-3.2 dB

TXFFE2-

RATIO

Transmitter FRL TXFFE2 de-emphasis

ratio.

At 12 Gbps FRL; TERM = 3h; HPD_IN =

H; TX_AC_EN = 0; CLK_TXFFE = 6h;

CLK_VOD = 3h; D0_TXFFE = 6h;

D0_VOD = 3h; D1_TXFFE = 6h; D1_VOD

= 3h; D2_TXFFE = 6h; D2_VOD = 3h; 20

* log (Vp/Vn); 128 zeros followed by 128

ones;

-3.5 dB

TXFFE3-

RATIO

Transmitter FRL TXFFE3 de-emphasis

ratio

At 12 Gbps FRL; TERM = 3h; HPD_IN =

H; TX_AC_EN = 0; CLK_TXFFE = 7h;

CLK_VOD = 3h; D0_TXFFE = 7h;

D0_VOD = 3h; D1_TXFFE = 7h; D1_VOD

= 3h; D2_TXFFE = 7h; D2_VOD = 3h; 20

* log (Vp/Vn); 128 zeros followed by 128

ones;

-4.5 dB

HDMI HIGH SPEED OUTPUTS (Linear Mode)

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6.5 Electrical Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LF-

TXSWG-0

Low-frequency 1-dB compression point

Dx_VOD = 0.

At 10 MHz; 200 mVpp < V

< 1200

mVpp; EQ0; DCGAIN = 0 dB; 12Gbps

CTLE; CTLEBYP_EN = 0; BERT TX 100

MHz clock starting at 200 mV to 1200

mV in 50 mV steps;TX DC coupled to

VCC_EXT;

900 mVpp

HF-

TXSWG-0

High-frequency 1-dB compression point

Dx_VOD = 0.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;

CTLEBYP_EN = 0; TX DC coupled to

VCC_EXT;

750 mVpp

LF-

TXSWG-R

Low-frequency 1-dB compression point

Dx_VOD = 1.

At 10 MHz; 200 mVpp < V

< 1200

mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps

CTLE; CTLEBYP_EN = 0; BERT TX 100

MHz clock starting at 200 mV to 1200

mV in 50 mV steps; TX DC coupled to

VCC_EXT;

1000 mVpp

HF-

TXSWG-R

High-frequency 1-dB compression point

Dx_VOD = 1.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12Gbps CTLE;

CTLEBYP_EN = 0;TX DC coupled to

VCC_EXT;

800 mVpp

LF-

TXSWG-F

Low-frequency 1-dB compression point

Dx_VOD = 2.

At 10 MHz; 200 mVpp < V

< 1200

mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps

CTLE; CTLEBYP_EN = 0; BERT TX 100

MHz clock starting at 200 mV to 1200

mV in 50 mV steps; TX DC coupled to

VCC_EXT;

1100 mVpp

HF-

TXSWG-F

High-frequency 1-dB compression point

Dx_VOD = 2.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;

CTLEBYP_EN = 0; TX DC coupled to

VCC_EXT;

875 mVpp

LF-

TXSWG-1

Low-frequency 1-dB compression point

Dx_VOD = 3.

At 10 MHz; 200 mVpp < V

< 1200

mVpp; EQ0; DCGAIN = 0 dB; 12 Gbps

CTLE; CTLEBYP_EN = 0; BERT TX 100

MHz clock starting at 200 mV to 1200

mV in 50 mV steps; TX DC coupled to

VCC_EXT;

1200 mVpp

HF-

TXSWG-1

High-frequency 1-dB compression point

Dx_VOD = 3.

At 6 GHz; 200 mVpp < V

< 1200 mVpp;

EQ0; DCGAIN = 0 dB; 12 Gbps CTLE;

CTLEBYP_EN = 0; TX DC coupled to

VCC_EXT;

950 mVpp

RCLKOUT

TX-CM

Output common mode voltage 2.4 2.8 3.465 V

ODPP

Peak-to-peak output voltage swing 600 700 1100 mV

TERM

Differential output impedance 70 100 120

Ω

Rise and fall time 20% to 80% 100 370 ps

TX_AC

Required external AC capacitor 8 10 12 nF

6.6 Timing Requirements

MIN NOM MAX UNIT

Local I2C (SCL/CFG0, SDA/CFG1). Refer to 图 7-9.

SCL

C clock frequency 1 MHz

BUF

Bus free time between START and STOP conditions 0.5 µs

HD_STA

Hold time after repeated START condition. After this period, the first clock

pulse is generated

0.26 µs

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6.6 Timing Requirements (continued)

MIN NOM MAX UNIT

LOW

Low period of the I

C clock 0.5 µs

HIGH

High period of the I

C clock 0.26 µs

SU_STA

Setup time for a repeated START condition 0.26 µs

HD_DAT

Data hold time 0

μs

SU_DAT

Data setup time 50 ns

Rise time of both SDA and SCL signals 120 ns

Fall time of both SDA and SCL signals 4 120 ns

SU_STO

Setup time for STOP condition 0.26

μs

DDC Snoop I2C Timings. Refer to 图 7-9.

SCL

C DDC clock frequency 100 kHz

BUF

Bus free time between START and STOP conditions 4.7 µs

HD_STA

Hold time after repeated START condition. After this period, the first clock

pulse is generated

4 µs

LOW

Low period of the I

C clock 4.7 µs

HIGH

High period of the I

C clock 4 µs

SU_STA

Setup time for a repeated START condition 4.7 µs

HD_DAT

Data hold time 0

μs

SUDAT

Data setup time 250 ns

Rise time of both SDA and SCL signals. Measured from 30% to 70%. 1000 ns

Fall time of both SDA and SCL signals Measured from 70% to 30%. 300 ns

SU_STO

Setup time for STOP condition 4

μs

b_LV

Capacitive load for each bus line on LV side 50 pF

Power-On. Refer to 图 7-1.

VCC_RAMP

supply ramp. Measured from 10% to 90%. 0.10 50 ms

D_PG

Internal POR de-assertion delay 5 ms

VIO_SU

supply stable before reset

(2)

high. 100 µs

CFG_SU

Configuration pins

(1)

setup before reset

(2)

high. 0 µs

CFG_HD

Configuration pins

(1)

hold after reset

(2)

high. 500 µs

(1) Follow comprise the configuration pins: MODE, ADDR/EQ0, EQ1, TXSWG, TXSLEW, TXPRE, AC_EN, HPDOUT_SEL, DCGAIN

(2) Reset is the logical AND of internal POR and EN pin.

6.7 Switching Characteristics

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Redriver

HDMI14_o

pen

Maximum HDMI 1.4 clock frequency at

which TX termination is assured to be

open

HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340

MHz; TXTERM_AUTO_HDMI14 = 0h;

TERM = 2h; TX is DC-coupled;

165 MHz

HDMI14_3

Minimum HDMI 1.4 clock frequency at

which TX termination is assured to be

300-ohms

HDMI1.4; 25 MHz ≤ IN_CLK ≤ 340

MHz; TXTERM_AUTO_HDMI14 = 0h;

TERM = 2h; TX is DC-coupled;

250 MHz

AEQ_DON

Time from start of FRL link training to

AEQ complete for 3 Gbps.

0.7 ms

AEQ_DON

Time from start of FRL link training to

AEQ complete for 6 Gbps, 8 Gbps, 10

Gbps, and 12 Gbps

0.5 ms

Propagation delay time At TTP4; 90 220 ps

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6.7 Switching Characteristics (continued)

over recommended voltage and operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SK1(T)

Clock lane Intra-pair output skew with

worse case skew at inputs

At TTP4; With 0.15 UI skew at input; At 6

Gbps with 150 MHz clock; TX termination

100-Ω; Linear mode;

0.15 UI

SK1(T)

Data lane Intra-pair output skew with

worse case skew at inputs

At TTP4; With 0.15 UI skew at input; At

12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX

termination 100-Ω; Linear mode;

0.15 UI

SK1(T)

Clock lane Intra-pair output skew with

zero intra-pair skew at inputs

At TTP4; No intra-pair skew at input; 6

Gbps with 150 MHz clock; TX termination

100-Ω; Limited mode;

0.10 0.15 UI

SK1(T)

Data lane Intra-pair output skew with zero

intra-pair skew at inputs

At TTP4; No intra-pair skew at input; At

12 Gbps; LTP5, 6, 7, or 8; TXFFE0; TX

termination 100-Ω; Limited mode;

0.053 0.11 UI

SK2(T)

Inter-pair output skew

At TTP4; At 12 Gbps; LTP5, 6, 7, or 8;

TXFFE0;

30 ps

RF-CLK-14

Transition time (rise and fall time) for

clock lane when operating at HDMI1.4

At TTP4; 20% to 80%; Clock Frequency =

300 MHz;

75 600 ps

RF-CLK-20

Transition time (rise and fall time) for

clock lane when operating at HDMI 2.0

At TTP4; 20% to 80%; Clock Frequency =

150 MHz;

75 600 ps

RF_14

Transition time (rise and fall time) for data

lanes when operating at HDMI 1.4

At TTP4; 20% to 80%; DR = 3 Gbps;

SLEW_HDMI14 = default; PRBS7

pattern; Clock Frequency = 300 MHz;

75 195 ps

RFDAT_20

Transition time (rise and fall time) for data

lanes when operating at HDMI 2.0

At TTP4; 20% to 80%; DR = 6 Gbps;

SLEW_HDMI20 = default; PRBS7

pattern; Clock Frequency = 150 MHz;

42.5 115 ps

SLEW_FRL

Single-ended TX slew rate for data lanes

when operating at HDMI 2.1 FRL

At TTP4; Slope at 50% level; All FRL DR

up to 12 Gbps; SLEW_HDMI21 = Default;

clock pattern of 128 zeros and 128 ones;

16 mV/ps

TRANS_3G

Transistion bit duration when de-