PSoC 4.4200 BLE平台数据手册：可编程系统芯片

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PSoC R 4 4200 BLE 家族数据手册是一款由 Cypress Semiconductor Corporation 开发的可编程系统级芯片（Programmable System-on-Chip, PSoC）产品系列。这款创新的平台架构集成了一个高效的 32 位 Arm Cortex-M0 处理器，其特点是单周期乘法运算和直接存储器访问 (DMA) 功能，这使得它在实时处理能力和效率上表现出色。该芯片提供了高达 256KB 的闪存存储，其中还包括读取加速器，以优化程序加载速度。 PSoC 4 4200 BLE 特别关注低功耗蓝牙 (BLE) 或蓝牙智能技术，将微控制器与内置的无线通信模块结合，形成了一个完整的 BLESS（Bluetooth Low Energy Subsystem）解决方案。这使得产品在物联网 (IoT) 设备中广泛应用于无线传感器网络、健身追踪器、智能家居控制等领域，能够提供长电池寿命和稳定的无线连接。此外，该芯片还配备了可编程数字逻辑，允许用户根据应用需求灵活定制电路功能。高精度的 12/16 位模拟-数字转换器 (ADC) 和具有比较模式的运算放大器进一步增强了信号处理能力。标准的通信和定时外围设备，如串行接口、定时器等，为集成多种通信协议和实现精确时间管理提供了便利。 PSoC 4 4200 BLE 的可重构性和现场可调性是其主要优势之一，设计者可以根据实际项目需求动态调整硬件配置，无需重新设计或更换硬件。这大大降低了开发成本和时间，提高了产品的适应性和竞争力。 PSoC R 4 4200 BLE 家族数据手册详细介绍了这款高度灵活且功能丰富的嵌入式系统控制器，其集成的高性能处理器、无线通信模块以及自定义能力使其成为物联网、无线传感器网络和消费电子应用的理想选择。通过深入理解这份数据手册，工程师可以充分利用这些特性来构建高效、低功耗的智能设备。

PSoC

4: 4200_BLE

Family Datasheet

Document Number: 002-23053 Rev. ** Page 9 of 49

Fixed-Function Digital

Timer/Counter/PWM Block

The timer/counter/PWM block consists of four 16-bit counters

with user-programmable period length. There is a Capture

may be an I/O event), a period register which is used to either

stop or auto-reload the counter when its count is equal to the

period register, and compare registers to generate compare

value signals which are used as PWM duty cycle outputs. The

block also provides true and complementary outputs with

programmable offset between them to allow the use as

deadband programmable complementary PWM outputs. It also

has a Kill input to force outputs to a predetermined state; for

example, this is used in motor-drive systems when an

overcurrent state is indicated and the PWMs driving the FETs

need to be shut off immediately with no time for software

intervention.

Serial Communication Blocks (SCB)

PSoC 4200_BL has two SCBs, each of which can implement an

C, UART, or SPI interface.

C Mode: The hardware I

C block implements a full

multi-master and slave interface (it is capable of multimaster

arbitration). This block is capable of operating at speeds of up to

1 Mbps (Fast Mode Plus) and has flexible buffering options to

reduce the interrupt overhead and latency for the CPU. It also

supports EzI

C that creates a mailbox address range in the

memory of PSoC 4200_BL and effectively reduces the I

communication to reading from and writing to an array in the

memory. In addition, the block supports an 8-deep FIFO for

receive and transmit, which, by increasing the time given for the

CPU to read the data, greatly reduces the need for clock

stretching caused by the CPU not having read the data on time.

The FIFO mode is available in all channels and is very useful in

the absence of DMA.

The I

C peripheral is compatible with I

C Standard-mode,

Fast-mode, and Fast-Mode Plus devices as defined in the NXP

C-bus specification and user manual (UM10204). The I

C bus

I/O is implemented with GPIO in open-drain modes.

SCB1 is fully compliant with Standard mode (100 kHz), Fast

mode (400 kHz), and Fast-Mode Plus (1 MHz) I

C signaling

specifications when routed to GPIO pins P5[0] and P5[1], except

for hot-swap capability during I

C active communication. The

remaining GPIOs do not meet the hot-swap specification (V

off; draw < 10-µA current) for Fast mode and Fast-Mode Plus,

Spec (20 mA) for Fast-Mode Plus, hysteresis spec (0.05 V

)

for Fast mode and Fast-Mode Plus, and minimum fall time spec

for Fast mode and Fast-Mode Plus.

■ GPIO cells, including P5.0 and P5.1, cannot be hot-swapped

or powered up independent of the rest of the I

C system.

■ The GPIO pins P5.0 and P5.1 are over-voltage tolerant but

cannot be hot-swapped or powered up independent of the rest

of the I

C system

■ Fast-Mode Plus has an I

specification of 20 mA at a V

0.4 V. The GPIO cells can sink a maximum of 8 mA I

with a

maximum of 0.6 V.

■ Fast-mode and Fast-Mode Plus specify minimum Fall times,

which are not met with the GPIO cell; the Slow-Strong mode

can help meet this spec depending on the bus load.

UART Mode: This is a full-feature UART operating at up to

1 Mbps. It supports automotive single-wire interface (LIN),

infrared interface (IrDA), and SmartCard (ISO7816) protocols, all

of which are minor variants of the basic UART protocol. In

addition, it supports the 9-bit multiprocessor mode that allows the

addressing of peripherals connected over common RX and TX

lines. Common UART functions such as parity error, break

detect, and frame error are supported. An 8-deep FIFO allows

much greater CPU service latencies to be tolerated. Note that

hardware handshaking is not supported. This is not commonly

used and can be implemented with a UDB-based UART in the

system, if required.

SPI Mode: The SPI mode supports full Motorola SPI, TI Secure

Simple Pairing (SSP) (essentially adds a start pulse that is used

to synchronize SPI Codecs), and National Microwire (half-duplex

form of SPI). The SPI block can use the FIFO for transmit and

receive.

GPIO

PSoC 4200_BL has 36 GPIOs. The GPIO block implements the

following:

■ Eight drive strength modes:

❐ Analog input mode (input and output buffers disabled)

❐ Input only

❐ Weak pull-up with strong pull-down

❐ Strong pull-up with weak pull-down

❐ Open drain with strong pull-down

❐ Open drain with strong pull-up

❐ Strong pull-up with strong pull-down

❐ Weak pull-up with weak pull-down

■ Input threshold select (CMOS or LVTTL)

■ Pins 0 and 1 of Port 5 are overvoltage-tolerant pins

■ Individual control of input and output buffer enabling/disabling

in addition to drive-strength modes

■ Hold mode for latching previous state (used for retaining the

I/O state in Deep Sleep and Hibernate modes)

■ Selectable slew rates for dV/dt-related noise control to improve

EMI

The pins are organized in logical entities called ports, which are

8-bit in width. During power-on and reset, the blocks are forced

to the disable state so as not to crowbar any inputs and/or cause

excess turn-on current. A multiplexing network known as a

high-speed I/O matrix (HSIOM) is used to multiplex between

various signals that may connect to an I/O pin. Pin locations for

fixed-function peripherals are also fixed to reduce internal multi-

plexing complexity (these signals do not go through the DSI

network). DSI signals are not affected by this and any pin may

be routed to any UDB through the DSI network.

Data output and pin-state registers store, respectively, the values

to be driven on the pins and the states of the pins themselves.

Every I/O pin can generate an interrupt if so enabled and each

I/O port has an interrupt request (IRQ) and interrupt service

routine (ISR) vector associated with it (5 for PSoC 4200_BL).

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