"MIPI DSI Specification 1.02版本详解与更新"

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MIPI DSI Specification 1.02版本是MIPI Alliance所发布的用于显示串行界面的规范，版本号为1.02.00 r0.07，日期为2010年3月30日。该规范是MIPI Alliance成员机构的机密信息，版权归MIPI Alliance所有。这个规范的起草版本是1.02.00修订0.07，发行日期是2010年3月30日。随着Display Working Group的工作继续进行，预计本文档将进行进一步的技术修改。这个规范为了满足行业对于显示界面技术的需求，MIPI Alliance进行了长期的研究和讨论，最终发布了该规范。根据MIPI DSI Specification 1.02版本，DSI可以理解为Display Serial Interface，是一种用于显示设备的串行接口规范。该规范的发布旨在满足市场需求，同时提高移动设备和其他显示设备的显示性能。MIPI Alliance成员机构通过制定该规范，旨在为移动设备和其他显示设备提供一种更加高效、灵活和节能的显示接口标准。 MIPI DSI Specification 1.02版本的发布得到了行业内外的高度关注和认可，其规范适用于电子设备制造商、显示技术提供商和其他相关行业的企业和机构。这个规范的发布将对显示技术领域产生重大的影响，为显示设备行业的发展提供了有力的支持。 MIPI DSI Specification 1.02版本的发布标志着MIPI Alliance对显示技术领域的深入研究和探索，为行业发展提供了重要的技术支持和标准规范。该规范的发布将有助于推动移动设备和其他显示设备的发展，提高其显示性能和使用体验。同时，这也将为相关行业的企业和机构提供更加稳定和可靠的显示技术支持，促进整个行业的健康发展。总的来说，MIPI DSI Specification 1.02版本对于显示技术领域来说具有重大的意义，其发布将有助于推动行业技术的进步和创新，为移动设备和其他显示设备的发展提供更加高效和灵活的显示接口标准。这个规范的发布标志着MIPI Alliance在显示技术领域的领先地位，为整个行业的发展注入了新的动力和活力。MIPI Alliance将继续致力于推动相关领域的技术创新和发展，为移动设备和其他显示设备的发展提供更加高效和可靠的技术支持。

Version 1.02.00 r0.07 30-Mar-2010 DRAFT MIPI Alliance Specification for DSI

MIPI Alliance Member Confidential.

before transmission to the display module. At the display, serial information is transformed back to parallel 418

data and control signals for the on-panel display controller. Similarly, the display module can return status 419

information and requested memory data to the host processor, using the same serial data path. 420

3.2 Display Pixel Interface Standard for Parallel Signaling (DPI-2) 421

DPI-2 is a MIPI Alliance standard for parallel interfaces to display modules without on-panel display 422

controller or frame buffer. These display modules rely on a steady flow of pixel data from host processor to 423

the display, to maintain an image without flicker or other visual artifacts. MIPI Alliance standards 424

document several pixel formats for Active Matrix (AM) display modules. 425

Like DBI-2, DPI-2 is a MIPI Alliance standard for parallel interfaces. The data path may be 16-, 18-, or 24-426

bits wide, depending on pixel format(s) supported by the display module. This document refers to DPI 427

mode of operation as Video Mode. 428

Some display modules that use Video Mode in normal operation also make use of a simplified form of 429

Command Mode, when in low-power state. These display modules can shut down the streaming video 430

interface and continue to refresh the screen from a small local frame buffer, at reduced resolution and pixel 431

depth. The local frame buffer shall be loaded, prior to interface shutdown, with image content to be 432

displayed when in low-power operation. These display modules can switch mode in response to power-433

control commands. 434

3.3 MIPI Alliance Specification for Display Command Set (DCS) 435

DCS is a MIPI Alliance specification for the command set used by DSI and DBI-2 standards. Commands 436

are sent from the host processor to the display module. On the display module, a display controller receives 437

and interprets commands, then takes appropriate action. Commands fall into four broad categories: read 438

parameters. 440

3.4 MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) 441

CSI-2 is a MIPI Alliance standard for serial interface between a camera module and host processor. It is 442

based on the same physical layer technology and low-level protocols as DSI. Some significant differences 443

between DSI and CSI-2 are: 444

• CSI-2 uses unidirectional high-speed Link, whereas DSI is half-duplex bidirectional Link 445

• CSI-2 makes use of a secondary channel, based on I

C, for control and status functions 446

CSI-2 data direction is from peripheral (Camera Module) to host processor, while DSI’s primary data 447

direction is from host processor to peripheral (Display Module). 448

3.5 MIPI Alliance Specification for D-PHY (D-PHY) 449

[MIPI04] provides the physical layer definition for DSI. Th

e functionality specified by the D-PHY 450

specification covers all electrical and timing aspects, as well as low-level protocols, signaling, and message 451

transmissions in various operating modes. 452

453

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4 DSI Introduction 454

DSI specifies the interface between a host processor and a peripheral such as a display module. It builds on 455

existing MIPI Alliance specifications by adopting pixel formats and command set specified in DPI-2, DBI-456

2 and DCS standards. 457

Figure 1 shows a simplified DSI interface. From a c

onceptual viewpoint, a DSI-compliant interface 458

performs the same functions as interfaces based on DBI-2 and DPI-2 standards or similar parallel display 459

interfaces. It sends pixels or commands to the peripheral, and can read back status or pixel information 460

from the peripheral. The main difference is that DSI serializes all pixel data, commands, and events that, in 461

traditional or legacy interfaces, are normally conveyed to and from the peripheral on a parallel data bus 462

with additional control signals. 463

From a system or software point of view, the serialization and deserialization operations should be 464

transparent. The most visible, and unavoidable, consequence of transformation to serial data and back to 465

parallel is increased latency for transactions that require a response from the peripheral. For example, 466

reading a pixel from the frame buffer on a display module has a higher latency using DSI than DBI. 467

Another fundamental difference is the host processor’s inability during a read transaction to throttle the 468

rate, or size, of returned data. 469

Host Device, e.g. an Application

Processor or Baseband Processor

containing HS Transmitter, LP

Transmitter, LP Receiver

Peripheral, e.g. a Display containing HS

Receiver, LP Receiver, optional LP

Transmitter (for bidirectional only)

DataN+

DataN-

Clock+

Clock-

Data0+

Data0-

Number of Data

Lanes may be

1, 2, 3, or 4

DataN+

DataN-

Clock+

Clock-

Data0+

Data0-

High Speed

Data Links

(Lane 0 may be

bidirectional in

LP Mode)

470

Figure 1 DSI Transmitter and Receiver Interface 471

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MIPI Alliance Member Confidential.

4.1 DSI Layer Definitions 472

Application

Low Level Protocol

Lane Management

PHY Layer

Pixel to Byte Packing Formats

Command Generation / Interpretation

Packet Based Protocol

ECC and Checksum Generation and

Testing

Lane Distribution and Merging

Start of Packet / End of Packet

Serializer / Deserializer

Clock Management (DDR)

Electrical Layer (SLVS)

Application

Low Level Protocol

Lane Management

PHY Layer

Application Processor Peripheral

Lane 0 – High Speed Data (optionally Bidirectional in LP Mode)

Data Control

Data Control Data Control

Data Control

Data ControlData Control

Data Control

Data

(N+1) x 8 bits

8bits

(N+1) x 8 bits

8bits

Control

High Speed Unidirectional Clock

Lane N – High Speed Unidirectional Data

473

Figure 2 DSI Layers 474

A conceptual view of DSI organizes the interface into several functional layers. A description of the layers 475

follows and is also shown in Figure 2. 476

PHY L

ayer: The PHY Layer specifies transmission medium (electrical conductors), the input/output 477

circuitry and the clocking mechanism that captures “ones” and “zeroes” from the serial bit stream. This part 478

of the specification documents the characteristics of the transmission medium, electrical parameters for 479

signaling and the timing relationship between clock and Data Lanes. 480

The mechanism for signaling Start of Transmission (SoT) and End of Transmission (EoT) is specified, as 481

well as other “out of band” information that can be conveyed between transmitting and receiving PHYs. 482

Bit-level and byte-level synchronization mechanisms are included as part of the PHY. Note that the 483

electrical basis for DSI (SLVS) has two distinct modes of operation, each with its own set of electrical 484

parameters. 485

The PHY layer is described in [MIPI04]. 486

ane Management Layer: DSI is Lane-scalable for increased performance. The number of data signals 487

may be 1, 2, 3, or 4 depending on the bandwidth requirements of the application. The transmitter side of the 488

interface distributes the outgoing data stream to one or more Lanes (“distributor” function). On the 489

Version 1.02.00 r0.07 30-Mar-2010 DRAFT MIPI Alliance Specification for DSI

MIPI Alliance Member Confidential.

receiving end, the interface collects bytes from the Lanes and merges them together into a recombined data 490

stream that restores the original stream sequence (“merger” function). 491

Protocol Layer: At the lowest level, DSI protocol specifies the sequence and value of bits and bytes 492

traversing the interface. It specifies how bytes are organized into defined groups called packets. The 493

protocol defines required headers for each packet, and how header information is generated and interpreted. 494

The transmitting side of the interface appends header and error-checking information to data being 495

transmitted. On the receiving side, the header is stripped off and interpreted by corresponding logic in the 496

receiver. Error-checking information may be used to test the integrity of incoming data. DSI protocol also 497

documents how packets may be tagged for interleaving multiple command or data streams to separate 498

destinations using a single DSI. 499

Application Layer: This layer describes higher-level encoding and interpretation of data contained in the 500

data stream. Depending on the display subsystem architecture, it may consist of pixels having a prescribed 501

format, or of commands that are interpreted by the display controller inside a display module. The DSI 502

specification describes the mapping of pixel values, commands and command parameters to bytes in the 503

packet assembly. See [MIPI01]. 504

4.2 Command and Video Modes 505

DSI-compliant peripherals support either of two basic modes of operation: Command Mode and Video 506

Mode. Which mode is used depends on the architecture and capabilities of the peripheral. The mode 507

definitions reflect the primary intended use of DSI for display interconnect, but are not intended to restrict 508

DSI from operating in other applications. 509

Typically, a peripheral is capable of Command Mode operation or Video Mode operation. Some Video 510

Mode display modules also include a simplified form of Command Mode operation in which the display 511

module may refresh its screen from a reduced-size, or partial, frame buffer, and the interface (DSI) to the 512

host processor may be shut down to reduce power consumption. 513

4.2.1 Command Mode 514

Command Mode refers to operation in which transactions primarily take the form of sending commands 515

and data to a peripheral, such as a display module, that incorporates a display controller. The display 516

controller may include local registers and a frame buffer. Systems using Command Mode write to, and read 517

from, the registers and frame buffer memory. The host processor indirectly controls activity at the 518

peripheral by sending commands, parameters and data to the display controller. The host processor can also 519

read display module status information or the contents of the frame memory. Command Mode operation 520

requires a bidirectional interface. 521

4.2.2 Video Mode Operation 522

Video Mode refers to operation in which transfers from the host processor to the peripheral take the form of 523

a real-time pixel stream. In normal operation, the display module relies on the host processor to provide 524

image data at sufficient bandwidth to avoid flicker or other visible artifacts in the displayed image. Video 525

information should only be transmitted using High Speed Mode. 526

Some Video Mode architectures may include a simple timing controller and partial frame buffer, used to 527

maintain a partial-screen or lower-resolution image in standby or Low Power Mode. This permits the 528

interface to be shut down to reduce power consumption. 529

To reduce complexity and cost, systems that only operate in Video Mode may use a unidirectional data 530

path. 531

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MIPI Alliance Member Confidential.

4.2.3 Virtual Channel Capability 532

While this specification only addresses the connection of a host processor to a single peripheral, DSI 533

incorporates a virtual channel capability for communication between a host processor and multiple, 534

physical display modules. . A bridge device may create multiple, separate connections to display modules 535

or other devices or a display module or device may support multiple virtual channels. Display modules are 536

completely independent, may operate simultaneously, and may be of different display architecture types, 537

limited only by the total bandwidth available over the shared DSI Link. The details of connecting multiple 538

peripherals to a single Link are beyond the scope of this document. 539

Since interface bandwidth is shared between peripherals, there are constraints that limit the physical extent 540

and performance of multiple-peripheral systems. 541

The DSI protocol permits up to four virtual channels, enabling traffic for multiple peripherals to share a 542

common DSI Link. For example, in some high-resolution display designs, multiple physical drivers serve 543

different areas of a common display panel. Each driver is integrated with its own display controller that 544

connects to the host processor through DSI. Using virtual channels, the display controller directs data to the 545

individual drivers, eliminating the need for multiple interfaces or complex multiplexing schemes. Virtual 546

channels may also be employed by devices where one channel is a bidirectional Command Mode channel 547

and the second channel is a Video Mode unidirectional channel. Virtual channels may be employed by a 548

display module or a DSI bridge device receiving interlaced video from the host-processor, where one 549

channel is corresponding to the first field and another channel is the second field of an interlaced video 550

frame. The DSI specification makes no requirements on the specific value assigned to each virtual channel 551

used to designate interlaced fields, For clarity, the first interlaced video field may be assigned as DI[7:6] = 552

0b00 and the second interlaced video field may be assigned DI[7:6] = 0b01. 553

554

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"MIPI DSI Specification 1.02版本详解与更新"

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