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Figures
Figure
Number Title
Page
Number
Figures xvii
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
7-5 e200z6 Branch Target Buffer...................................................................................... 7-8
7-6 Updating Branch History ............................................................................................ 7-9
7-7 Pipelining—Execute and Write Back Stages.............................................................. 7-9
7-8 Basic Pipeline Flow, Single-Cycle Instructions........................................................ 7-12
7-9 Basic Pipeline Flow, Load and Store Instructions .................................................... 7-13
7-10 Basic Pipeline Flow, Branch Instructions ................................................................. 7-13
7-11 Basic Pipeline Flow, Branch Speculation ................................................................. 7-13
7-12 Basic Pipeline Flow, Multiple-Cycle Instructions .................................................... 7-14
7-13 Pipelined Load/Store Instructions............................................................................. 7-14
7-14 Pipelined Load/Store Instructions with Wait-State................................................... 7-15
7-15 Pipelined Load Instructions with Load Target Data Dependency ............................ 7-15
7-16 Pipelined Instructions with Base Register Update Data Dependency ...................... 7-16
7-17 mtspr, mfspr Instruction Execution - (1)................................................................... 7-16
7-18 mtmsr, wrtee, and wrteei Execution ....................................................................... 7-17
7-19 Cache/MMU mtspr, mfspr, and MMU Instruction Execution................................ 7-18
7-20 Interrupt Recognition and Exception Processing Timing ......................................... 7-20
7-21 Interrupt Recognition and Handler Instruction Execution—Load/Store
in Progress............................................................................................................ 7-21
7-22 Interrupt Recognition and Handler Instruction Execution—Multiple-Cycle
Instruction Abort .................................................................................................. 7-22
8-1 e200z6 Signal Groups................................................................................................. 8-3
8-2 Example External JTAG Register Design................................................................. 8-29
8-3 Basic Read Transfer—Single-cycle Reads, Full Pipelining ..................................... 8-33
8-4 Read with Wait-State, Single-Cycle Reads, Full Pipelining..................................... 8-35
8-5 Basic Write Transfers—Single-Cycle Writes, Full Pipelining.................................. 8-36
8-6 Write with Wait-state, Single-Cycle Writes, Full Pipelining .................................... 8-37
8-7 Single-Cycle Reads, Single-Cycle Write, Full Pipelining ........................................ 8-38
8-8 Single-Cycle Read, Write, Read—Full Pipelining.................................................... 8-39
8-9 Multiple-Cycle Reads with Wait-State, Single-Cycle Writes, Full Pipelining ......... 8-40
8-10 Multi-Cycle Read with Wait-State, Single-cycle write, Read with Wait-State,
Single-Cycle Write, Full Pipelining..................................................................... 8-41
8-11 Misaligned Read, Read, Full Pipelining ................................................................... 8-42
8-12 Misaligned Write, Write, Full Pipelining.................................................................. 8-43
8-13 Misaligned Write, Single Cycle Read Transfer, Full Pipelining............................... 8-44
8-14 Burst Read Transfer .................................................................................................. 8-45
8-15 Burst Read with Wait-State Transfer......................................................................... 8-46
8-16 Burst Write Transfer.................................................................................................. 8-47
8-17 Burst Write with Wait-State Transfer........................................................................ 8-47
8-18 Read and Write Transfers: Instruction Read with Error, Data Read, Write, Full
Pipelining ............................................................................................................. 8-48
8-19 Data Read with Error, Data Write Retracted, Instruction Read, Full Pipelining ...... 8-50