PowerPC e200z6 处理器核心参考手册

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"e200z6.pdf是关于Freescale Semiconductor公司生产的e200z6 PowerPC处理器家族的参考手册，发布于2004年6月，提供了该系列处理器的技术细节和设计用途。" e200z6处理器家族是PowerPC架构的一个低成本实现，特别针对深度嵌入式控制应用而设计。这些处理器旨在提供经济高效的解决方案，而非追求极致性能。PowerPC Book E架构是IBM、Motorola和Apple共同开发的一种精简指令集计算机（RISC）架构，广泛应用于各种工业和嵌入式系统。 e200z6处理器的核心特性可能包括以下几点： 1. 低功耗：由于目标应用领域的特殊性，e200z6设计时考虑了低功耗的需求，这使得它适用于电池供电或对能源效率有严格要求的设备。 2. 高效能：虽然不是面向高性能计算，但e200z6仍然提供了一定程度的处理能力，能满足许多嵌入式系统的运算需求。 3. 嵌入式控制：这个处理器家族适合于实时控制系统，如汽车电子、工业自动化和家用电器等场景，它们需要快速响应时间和可靠的性能。 4. 精简功能：为了降低成本，e200z6可能简化了一些非必要的功能模块，如浮点运算单元，但保留了核心的指令集和控制逻辑。 5. 外围接口：处理器通常会集成一些常见的外围接口，如串行端口、定时器、中断控制器等，以便与外部硬件设备通信。手册中的"e200z6RM"可能代表“参考手册”（Reference Manual），这是开发者和工程师了解和使用e200z6处理器的重要文档，其中涵盖了指令集、寄存器映射、时序图、中断处理、调试工具等相关信息。 Freescale Semiconductor是一家知名的半导体制造商，后来被NXP Semiconductors收购。在手册提供的联系方式中，用户可以通过电子邮件、电话或邮寄方式获取技术支持和服务，包括在美国、欧洲、中东、非洲、日本和亚太地区的服务信息。 e200z6是Freescale Semiconductor的一款针对嵌入式市场的PowerPC处理器，它以低功耗、成本效益和足够的处理能力为特点，适用于需要控制功能且对成本敏感的应用环境。手册提供了详尽的技术细节，是开发和维护基于e200z6系统的关键参考资料。

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xvi e200z6 PowerPC Core Reference Manual

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

2-33 Debug Control Register 1 (DBCR1)......................................................................... 2-40

2-34 DBCR2 Register ....................................................................................................... 2-42

2-35 DBCR3 Register ....................................................................................................... 2-46

2-36 DBSR Register.......................................................................................................... 2-50

2-37 Hardware Implementation-Dependent Register 0 (HID0)........................................ 2-52

2-38 Hardware Implementation-Dependent Register 1 (HID1)........................................ 2-54

2-39 Branch Unit Control and Status Register (BUCSR) ................................................. 2-55

2-40 L1 Cache Control and Status Register 0 (L1CSR0).................................................. 2-56

2-41 L1 Cache Configuration Register 0 (L1CFG0)......................................................... 2-58

2-42 L1 Flush/Invalidate Register (L1FINV0) ................................................................. 2-59

2-43 MMU Control and Status Register 0 (MMUCSR0) ................................................. 2-60

2-44 MMU Configuration Register 1 (MMUCFG) .......................................................... 2-60

2-45 TLB Configuration Register 0 (TLB0CFG) ............................................................. 2-61

2-46 TLB Configuration Register 1 (TLB1CFG) ............................................................. 2-62

2-47 MAS Register 0 (MAS0) Format.............................................................................. 2-63

2-48 MMU Assist Register 1 (MAS1) .............................................................................. 2-63

2-49 MMU Assist Register 2 (MAS2) .............................................................................. 2-64

2-50 MMU Assist Register 3 (MAS3) .............................................................................. 2-65

2-51 MMU Assist Register 4 (MAS4) .............................................................................. 2-66

2-52 MMU Assist Register 6 (MAS6))............................................................................. 2-67

2-53 Process ID Register (PID0)....................................................................................... 2-67

2-54 Context Control Register (CTXCR) ......................................................................... 2-68

4-1 e200z6 Unified Cache................................................................................................. 4-2

4-2 Cache Organization and Line Format ......................................................................... 4-3

4-3 Cache Tag Format ....................................................................................................... 4-3

4-4 32-Kbyte Cache Lookup Flow.................................................................................... 4-5

4-5 CDACNTL Register ................................................................................................. 4-19

4-6 Cache Debug Access Data Register (CDADATA) ................................................... 4-20

5-1 Machine State Register (MSR) ................................................................................... 5-5

5-2 Interrupt Vector Prefix Register (IVPR) ..................................................................... 5-8

5-3 Interrupt Vector Offset Registers (IVOR)................................................................... 5-8

6-1 Effective-to-Real Address Translation Flow............................................................... 6-3

6-2 Virtual Address and TLB-Entry Compare Process..................................................... 6-5

6-3 Granting of Access Permission................................................................................... 6-6

6-4 e200z6 TLB1 Organization......................................................................................... 6-7

6-5 Victim Selection.......................................................................................................... 6-8

6-6 MMU Assist Registers Summary ............................................................................. 6-17

7-1 e200z6 Block Diagram................................................................................................ 7-1

7-2 Seven-Stage Instruction Pipeline ................................................................................ 7-4

7-3 Pipeline........................................................................................................................ 7-5

7-4 e200z6 Instruction Buffer ........................................................................................... 7-7

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Figures xvii

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

7-5 e200z6 Branch Target Buffer...................................................................................... 7-8

7-6 Updating Branch History ............................................................................................ 7-9

7-7 Pipelining—Execute and Write Back Stages.............................................................. 7-9

7-8 Basic Pipeline Flow, Single-Cycle Instructions........................................................ 7-12

7-9 Basic Pipeline Flow, Load and Store Instructions .................................................... 7-13

7-10 Basic Pipeline Flow, Branch Instructions ................................................................. 7-13

7-11 Basic Pipeline Flow, Branch Speculation ................................................................. 7-13

7-12 Basic Pipeline Flow, Multiple-Cycle Instructions .................................................... 7-14

7-13 Pipelined Load/Store Instructions............................................................................. 7-14

7-14 Pipelined Load/Store Instructions with Wait-State................................................... 7-15

7-15 Pipelined Load Instructions with Load Target Data Dependency ............................ 7-15

7-16 Pipelined Instructions with Base Register Update Data Dependency ...................... 7-16

7-17 mtspr, mfspr Instruction Execution - (1)................................................................... 7-16

7-18 mtmsr, wrtee, and wrteei Execution ....................................................................... 7-17

7-19 Cache/MMU mtspr, mfspr, and MMU Instruction Execution................................ 7-18

7-20 Interrupt Recognition and Exception Processing Timing ......................................... 7-20

7-21 Interrupt Recognition and Handler Instruction Execution—Load/Store

in Progress............................................................................................................ 7-21

7-22 Interrupt Recognition and Handler Instruction Execution—Multiple-Cycle

Instruction Abort .................................................................................................. 7-22

8-1 e200z6 Signal Groups................................................................................................. 8-3

8-2 Example External JTAG Register Design................................................................. 8-29

8-3 Basic Read Transfer—Single-cycle Reads, Full Pipelining ..................................... 8-33

8-4 Read with Wait-State, Single-Cycle Reads, Full Pipelining..................................... 8-35

8-5 Basic Write Transfers—Single-Cycle Writes, Full Pipelining.................................. 8-36

8-6 Write with Wait-state, Single-Cycle Writes, Full Pipelining .................................... 8-37

8-7 Single-Cycle Reads, Single-Cycle Write, Full Pipelining ........................................ 8-38

8-8 Single-Cycle Read, Write, Read—Full Pipelining.................................................... 8-39

8-9 Multiple-Cycle Reads with Wait-State, Single-Cycle Writes, Full Pipelining ......... 8-40

8-10 Multi-Cycle Read with Wait-State, Single-cycle write, Read with Wait-State,

Single-Cycle Write, Full Pipelining..................................................................... 8-41

8-11 Misaligned Read, Read, Full Pipelining ................................................................... 8-42

8-12 Misaligned Write, Write, Full Pipelining.................................................................. 8-43

8-13 Misaligned Write, Single Cycle Read Transfer, Full Pipelining............................... 8-44

8-14 Burst Read Transfer .................................................................................................. 8-45

8-15 Burst Read with Wait-State Transfer......................................................................... 8-46

8-16 Burst Write Transfer.................................................................................................. 8-47

8-17 Burst Write with Wait-State Transfer........................................................................ 8-47

8-18 Read and Write Transfers: Instruction Read with Error, Data Read, Write, Full

Pipelining ............................................................................................................. 8-48

8-19 Data Read with Error, Data Write Retracted, Instruction Read, Full Pipelining ...... 8-50

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xviii e200z6 PowerPC Core Reference Manual

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

8-20 Misaligned Write with Error, Data Write Retracted, Burst Read Substituted, Full

Pipelining ............................................................................................................. 8-51

8-21 Burst Read with Error Termination, Burst Write ...................................................... 8-52

8-22 Wakeup Control Signal (p_wakeup)........................................................................ 8-52

8-23 Interrupt Interface Input Signals ............................................................................... 8-53

8-24 Interrupt Pending Operation...................................................................................... 8-53

8-25 Interrupt Acknowledge Operation ............................................................................ 8-54

8-26 Interrupt Acknowledge Operation—2 ...................................................................... 8-55

9-1 Power Management State Diagram............................................................................. 9-2

10-1 e200z6 Debug Resources.......................................................................................... 10-4

10-2 OnCE TAP Controller and Registers ...................................................................... 10-12

10-3 OnCE Controller as an FSM................................................................................... 10-13

10-4 e200z6 OnCE Controller and Serial Interface ........................................................ 10-17

10-5 OnCE Status Register (OSR) .................................................................................. 10-18

10-6 OnCE Command Register (OCMD)....................................................................... 10-19

10-7 OnCE Control Register........................................................................................... 10-21

10-8 CPU Scan Chain Register (CPUSCR) .................................................................... 10-26

10-9 Control State Register (CTL).................................................................................. 10-27

10-10 OnCE PC FIFO....................................................................................................... 10-31

11-1 Nexus3 Functional Block Diagram........................................................................... 11-4

11-2 Client Select Control Register................................................................................. 11-10

11-3 Port Configuration Register .....................................................................................11-11

11-4 Development Control Register 1 (DC1) ................................................................. 11-12

11-5 Development Control Register 2 (DC2) ................................................................. 11-13

11-6 Development Status Register (DS) ......................................................................... 11-14

11-7 Read/Write Access Control/Status Register (RWCS)............................................. 11-15

11-8 Read/Write Access Data Register (RWD) .............................................................. 11-16

11-9 Read/Write Access Address Register (RWA) ......................................................... 11-16

11-10 Watchpoint Trigger Register (WT) ......................................................................... 11-17

11-11 Data Trace Control Register (DTC)........................................................................ 11-18

11-12 Data Trace Start Address Registers 1 and 2 (DTSAn)............................................ 11-19

11-13 Data Trace End Address Registers 1 and 2 (DTEA

n) ............................................ 11-19

11-14 Nexus3 Register Access through JTAG/OnCE (Example)..................................... 11-20

11-15 Ownership Trace Message Format.......................................................................... 11-22

11-16 Error Message Format............................................................................................. 11-22

11-17 Indirect Branch Message (History) Format ............................................................ 11-26

11-18 Indirect Branch Message Format ............................................................................ 11-26

11-19 Direct Branch Message Format............................................................................... 11-26

11-20 Resource Full Message Format............................................................................... 11-27

11-21 Debug Status Message Format................................................................................ 11-27

11-22 Program Correlation Message Format .................................................................... 11-27

Figures

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Figures xix

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

11-23 Error Message Format............................................................................................. 11-28

11-24 Direct/Indirect Branch with Synchronization Message Format.............................. 11-29

11-25 Indirect Branch History with Synchronization Message Format............................ 11-29

11-26 Relative Address Generation and Re-Creation Example........................................ 11-30

11-27 Program Trace—Indirect Branch Message (Traditional)........................................ 11-32

11-28 Program Trace—Indirect Branch Message (History) ............................................. 11-32

11-29 Program Trace—Direct Branch (Traditional) and Error Messages ........................ 11-33

11-30 Program Trace—Indirect Branch with Synchronization Message.......................... 11-33

11-31 Data Write Message Format.................................................................................... 11-34

11-32 Data Read Message Format .................................................................................... 11-34

11-33 Error Message Format............................................................................................. 11-35

11-34 Data Write/Read with Synchronization Message Format....................................... 11-36

11-35 Data Trace—Data Write Message........................................................................... 11-39

11-36 Data Trace—Data Read with Synchronization Message........................................ 11-39

11-37 Error Message (Data Trace Only Encoded)............................................................ 11-39

11-38 Watchpoint Message Format................................................................................... 11-40

11-40 Watchpoint Message and Watchpoint Error Message............................................. 11-41

11-39 Error Message Format............................................................................................. 11-41

11-41 Error Message Format............................................................................................. 11-47

11-42 Single-Pin MSEO Transfers.................................................................................... 11-50

11-43 Dual-Pin MSEO Transfers ...................................................................................... 11-51

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