MDIN-3xx系列：集成HDMI发射器与VGA转换的高清视频处理器数据手册

需积分: 44 24 浏览量更新于2024-07-22 收藏 1.66MB PDF 举报

MDIN-3xx是一款由Macro Image Technology, Inc.设计的全高清视频显示处理器，集成了嵌入式SDRAM和HDMI发射器，以及三个10位视频DAC（数字模拟转换器）。这款单芯片解决方案专为视频解交错和格式转换而生，旨在提供高度集成的硬件平台，适用于对图像质量有高要求的应用场景。该系列产品的核心特性包括： 1. **视频处理功能**：MDIN-3xx支持数字视频输入，可以处理包括逐行扫描（Progressive Scan）和隔行扫描（Interlaced Scan）在内的多种视频类型，确保了对不同来源视频信号的兼容性。 2. **HDMI传输器**：内置HDMI发射器允许处理器将视频信号转换为符合HDMI标准的数字信号，这意味着它可以连接到HDMI显示器，实现无损的高清视频传输，支持高达1080p分辨率和10位色彩深度，提供了出色的图像质量和音频性能。 3. **SDRAM集成**：处理器内部集成了SDRAM，这有助于优化数据存储和处理效率，减少了外部接口的需求，并可能支持实时处理更大的视频流。 4. **视频解交错和格式转换**：由于内置了专用的解交错引擎，MDIN-3xx能够处理隔行扫描视频，将其转换为逐行扫描格式，这对于某些需要流畅平滑画面的设备至关重要。 5. **配置灵活性**：MDIN-3xx系列提供了可配置的输入端口，用户可以根据实际应用需求调整视频输入格式和性能参数，增加系统的适应性和通用性。 6. **版权保护**：使用这份数据手册时需注意，未经Macro Image Technology, Inc.的明确书面许可，复制、分发或公开展示文档都是严格禁止的，表明其知识产权保护的重要性。 MDIN-3xx系列作为一款专业级视频处理芯片，广泛应用于消费电子、工业自动化、医疗成像以及其他需要高质量视频信号转换的领域，通过其高效能和灵活的架构，简化了系统设计并提升了整体系统的性能和稳定性。在购买和使用时，务必遵循制造商提供的最新版本规格和限制条件。

MDIN-3xx

Datasheet Version 0.5

Macro Image Technology, Inc. Confidential

1.2 I/O Signal Descriptions

1.2.1 MDIN-325 I/O Signal Descriptions

Group Signal Name I/O Description

Global RESET_N I

Global reset, Active low (5V tolerant & Schmitt trigger)

All the internal registers are set to default values.

CLK_A I

Input port A video clock

HACTIVE_A I

Input port A horizontal active or sync signal

Both active low and active high horizontal sync signal can be

acceptable.

This signal can be composite sync.

VACTIVE_A I

Input port A vertical active or sync signal

Both active low and active high vertical sync signal can be acceptable.

FIELDID_A I

Input port A field ID signal

Both active low and active high field identification signal can be

acceptable.

DATA_IN(23:0) I

Video data Input for input port A and B

These bits are configurable, 24-bit RGB/YCbCr 4:4:4, 20-bit YCbCr

4:2:2 or dual 10-bit YC-multiplexed 4:2:2 data can be input.

Video Input

CLK_B I

Input port B video clock

VCLK_OUT O

Output video pixel clock

This pin outputs the same clock as the internal video output clock with

certain amount of delay. The amount of delay can be programmable by

internal registers.

VCLK_OUT_B O

Additional output video pixel clock

The polarity and the amount of delay can be programmable by internal

registers.

This clock can be used to output an inverted video clock.

HSYNC_OUT O

Horizontal sync or active for output video data

Active high or active low can be selected by internal register.

VSYNC_OUT O

Vertical sync or active for output video data

Active high or active low can be selected by internal register.

DE_OUT O

Data enable for output video data

This signal can be horizontal active or composite sync.

Active high or active low can be selected by internal register.

Video Output

DATA_OUT(23:0) O

Digital video data output

24-bit RGB/YCbCr 4:4:4, 20-bit YCbCr 4:2:2 or 10-bit YC-multiplexed

4:2:2 data can be output.

SCL I

C bus clock (5V tolerant & Schmitt trigger)

SDA I/O

C bus data (5V tolerant & Schmitt trigger)

INT_OUT O

Interrupt output (active low or high)

Host Interface

I2C_MODE I

C bus 16-bit mode selection input

When open or high, the 16-bit mode (MDIN-2xx compatible) is

selected. When low, the 8-bit mode is selected.

TEST_MODE(3) I

Test mode control input

For normal operation this pin should be low.

TEST_MODE(2:1) I

Used to select the host interface clock. Normally, connect both pins to

GND and XTAL_IN will be used as the host interface clock.

Test Mode

TEST_MODE(0) I

Used as the LSB of I

C slave device address.

Table 1-1. MDIN-325 I/O Signal Descriptions

MDIN-3xx

Datasheet Version 0.5

Macro Image Technology, Inc. Confidential

Group Signal Name I/O Description

GPIO(36:0) I/O

General purpose input and output

GPIO

(*1)

GPO(2:0) O

General purpose output on sync output pins

SPI_CLK O

Clock output to an SPI slave device

SPI_CE_N O

Chip enable output to an SPI slave device

SPI_DO O

Data output to an SPI slave device

SPI Interface

(*2)

SPI_DI I

Data input from an SPI slave device

XTAL_IN I

External crystal input

Either crystal or oscillator can be used for this input pin.

XTAL_OUT O

External crystal output

VCLK_PLL_LF O

VCLK PLL loop filter

This pin must be connected to external low pass filter.

VCLK_PLL_AVDD33 VDD

VCLK PLL analog power (3.3V)

VCLK_PLL_AGND33 GND

VCLK PLL analog ground (3.3V)

VCLK_PLL_AVDD12 VDD

VCLK PLL analog power (1.2V)

VCLK_PLL_AGND12 GND

VCLK PLL analog ground (1.2V)

MCLK_PLL_AVDD12 VDD

MCLK PLL analog power (1.2V)

PLL

MCLK_PLL_AGND12 GND

MCLK PLL analog ground

DAC_GOUT AO

Analog green or Y output from 10-bit internal DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

DAC_BOUT AO

Analog blue or Pb output from 10-bit internal DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

DAC_ROUT AO

Analog red or Pr output from 10-bit internal DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

DAC_FSADJ AI

Full-scale output current adjust

The full-scale current on each output channel is determined by the

value of a resistor connected between this pin and analog ground.

DAC_VREF AI

Reference voltage input

Well regulated 1.2V reference voltage must be externally supplied. A

0.1uF ceramic capacitor must be connected between this pin and

analog ground.

DAC_AVDD33 VDD

Analog 3.3V power supply for each internal DAC channel

DAC

DAC_AGND GND

Analog ground for each internal DAC channel

VENC_OUT AO

Analog output from internal video encoder DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

VENC_FSADJ AI

Full-scale output current adjust

The full-scale current on the output is determined by the value of a

resistor connected between this pin and analog ground.

VENC_VREF AI

Reference voltage input

Well regulated 1.2V reference voltage must be externally supplied. A

0.1uF ceramic capacitor must be connected between this pin and

analog ground.

VENC_AVDD33 VDD

Analog 3.3V power supply for VENC DAC

Video Encoder

DAC

VENC_AGND GND

Analog ground for VENC DAC

VDD12 VDD

Digital 1.2V power supply for the core logic

VDD18 VDD

Digital 1.8V power supply for the SDRAM interface

VDD33 VDD

Digital 3.3V power supply for the I/O

Power &

Ground

GND GND

Digital ground

Note 1) GPIO signals are shared with other pins.

Note 2) SPI interface signals are shared with other pins.

Table 1-1. MDIN-325 I/O Signal Descriptions (Continued)

MDIN-3xx

Datasheet Version 0.5

Macro Image Technology, Inc. Confidential

1.2.2 MDIN-340 I/O Signal Descriptions

Group Signal Name I/O Description

Global RESET_N I

Global reset, Active low (5V tolerant & Schmitt trigger)

All the internal registers are set to default values.

CLK_A I

Input port A video clock

HACTIVE_A I

Input port A horizontal active or sync signal

Both active low and active high horizontal sync signal can be

acceptable.

This signal can be composite sync.

VACTIVE_A I

Input port A vertical active or sync signal

Both active low and active high vertical sync signal can be acceptable.

FIELDID_A I

Input port A field ID signal

Both active low and active high field identification signal can be

acceptable.

DATA_IN(23:0) I

Input port for video data

These bits are configurable, 24-bit RGB/YCbCr 4:4:4, 20-bit YCbCr

4:2:2 or 10-bit YC-multiplexed 4:2:2 data can be input.

Video Input

CLK_B I

Input port B video clock

MCLK_IN I

Audio input master clock for HDMI transmitter

SCK_IN I

S serial clock for HDMI transmitter

WS_IN I

S serial word select for HDMI transmitter

SD_IN(3:0) I

S serial audio data for HDMI transmitter

Audio Input

SPDIF_IN I

S/PDIF audio input for HDMI transmitter

HSYNC_OUT O

Horizontal sync or active for output video data

Active high or active low can be selected by internal register.

Sync Output

VSYNC_OUT O

Vertical sync or active for output video data

Active high or active low can be selected by internal register.

SCL I

C bus clock (5V tolerant & Schmitt trigger)

SDA I/O

C bus data (5V tolerant & Schmitt trigger)

INT_OUT O

Interrupt output (active low or high)

Host Interface

I2C_MODE I

C bus 16-bit mode selection input

When open or high, the 16-bit mode (MDIN-2xx compatible) is

selected. When low, the 8-bit mode is selected.

TEST_MODE(3) I

Test mode control input

For normal operation this pin should be low.

TEST_MODE(2:1) I

Used to select the host interface clock. Normally, connect both pins to

GND and XTAL_IN will be used as the host interface clock.

Test Mode

TEST_MODE(0) I

Used as the LSB of I

C slave device address.

SD_DQM I

SDRAM DQM input (should be tied to GND)

SDRAM

SD_CKE I

SDRAM CKE input (should be tied to VDD18)

GPIO(36:20) I/O

General purpose input and output

GPIO

(*1)

GPO(2:1) O

General purpose output on sync output pins

SPI_CLK O

Clock output to an SPI slave device

SPI_CE_N O

Chip enable output to an SPI slave device

SPI_DO O

Data output to an SPI slave device

SPI Interface

(*2)

SPI_DI I

Data input from an SPI slave device

Note 1) GPIO signals are shared with other pins.

Note 2) SPI interface signals are shared with other pins.

Table 1-2. MDIN-340 I/O Signal Descriptions

MDIN-3xx

Datasheet Version 0.5

Macro Image Technology, Inc. Confidential

Group Signal Name I/O Description

XTAL_IN I

External crystal input

Either crystal or oscillator can be used for this input pin.

XTAL_OUT O

External crystal output

VCLK_PLL_LF O

VCLK PLL loop filter

This pin must be connected to external low pass filter.

VCLK_PLL_AVDD33 VDD

VCLK PLL analog power (3.3V)

VCLK_PLL_AGND33 GND

VCLK PLL analog ground (3.3V)

VCLK_PLL_AVDD12 VDD

VCLK PLL analog power (1.2V)

VCLK_PLL_AGND12 GND

VCLK PLL analog ground (1.2V)

MCLK_PLL_AVDD12 VDD

MCLK PLL analog power (1.2V)

PLL

MCLK_PLL_AGND12 GND

MCLK PLL analog ground

DAC_GOUT AO

Analog green or Y output from 10-bit internal DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

DAC_BOUT AO

Analog blue or Pb output from 10-bit internal DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

DAC_ROUT AO

Analog red or Pr output from 10-bit internal DAC

It can drive a doubly terminated 75Ω load (37.5Ω equivalent load)

DAC_FSADJ AI

Full-scale output current adjust

The full-scale current on each output channel is determined by the

value of a resistor connected between this pin and analog ground.

DAC_VREF AI

Reference voltage input

Well regulated 1.2V reference voltage must be externally supplied. A

0.1uF ceramic capacitor must be connected between this pin and

analog ground.

DAC_AVDD33 VDD

Analog 3.3V power supply for each internal DAC channel

DAC

DAC_AGND GND

Analog ground for each internal DAC channel

HDMI_EXP(2:0),

HDMI_EXN(2:0)

TMDS output data pair

HDMI_EXCP,

HDMI_EXCN

TMDS output clock pair

HDMI_HPD I

Hot plug detect input (5V tolerant)

HDMI_DSCL O

DDC bus clock (5V tolerant)

HDMI_DSDA I/O

DDC bus data (5V tolerant & Schmitt trigger)

HDMI_CEC I/O

CEC bus (Schmitt trigger & open drain)

HDMI_TEST_MODE I

Test mode control input for HDMI PHY

For normal operation this pin should be low.

HDMI_TEST_XRST I

Test mode reset input for HDMI PHY

For normal operation this pin should be high.

TMDS_VDN12 VDD

TMDS analog power supply (1.2V)

TMDS_VDP33 VDD

TMDS analog power supply (3.3V)

HDMI Interface

TMDS_VSN GND

TMDS analog ground

Test Output VCLK_OUT O

Test output of internal video pixel clock

VDD12 VDD

Digital 1.2V power supply for the core logic

VDD18 VDD

Digital 1.8V power supply for the SDRAM interface

VDD33 VDD

Digital 3.3V power supply for the I/O

Power &

Ground

GND GND

Digital ground

Table 1-2. MDIN-340 I/O Signal Descriptions (Continued)

MDIN-3xx

Datasheet Version 0.5

Macro Image Technology, Inc. Confidential

1.2.3 MDIN-380 I/O Signal Descriptions

Group Signal Name I/O Description

Global RESET_N I

Global reset, Active low (5V tolerant & Schmitt trigger)

All the internal registers are set to default values.

CLK_A I

Input port A video clock

HACTIVE_A I

Input port A horizontal active or sync signal

Both active low and active high horizontal sync signal can be

acceptable.

This signal can be composite sync.

VACTIVE_A I

Input port A vertical active or sync signal

Both active low and active high vertical sync signal can be acceptable.

FIELDID_A I

Input port A field ID signal

Both active low and active high field identification signal can be

acceptable.

D_IN(35:0) I

Input port for video data

These bits are configurable, 36/30/24-bit RGB/YCbCr 4:4:4, 24/20/16-

bit YCbCr 4:2:2 or 12/10/8-bit YC-multiplexed 4:2:2 data can be input.

D_IN(25:0) are multi-function pins. D_IN(2), D_IN(1), D_IN(0) can also

be used as HACT_B, VACT_B, FID_B respectively.

Video Input

CLK_B I

Input port B video clock

MCLK_IN I

Audio input master clock for HDMI transmitter

SCK_IN I

S serial clock for HDMI transmitter

WS_IN I

S serial word select for HDMI transmitter

SD_IN(3:0) I

S serial audio data for HDMI transmitter

Audio Input

SPDIF_IN I

S/PDIF audio input for HDMI transmitter

VCLK_OUT O

Output video pixel clock

This pin outputs the same clock as the internal video output clock with

certain amount of delay. The amount of delay can be programmable by

internal registers.

VCLK_OUT_B O

Additional output video pixel clock

The polarity and the amount of delay can be programmable by internal

registers.

This clock can be used to output an inverted video clock.

HSYNC_OUT O

Horizontal sync or active for output video data

Active high or active low can be selected by internal register.

VSYNC_OUT O

Vertical sync or active for output video data

Active high or active low can be selected by internal register.

DE_OUT O

Data enable for output video data

This signal can be horizontal active or composite sync.

Active high or active low can be selected by internal register.

Video Output

D_OUT(7:0) O

Digital video data output

30/24-bit RGB/YCbCr 4:4:4, 20/16-bit YCbCr 4:2:2 or 10/8-bit YC-

multiplexed 4:2:2 data can be output from D_OUT(7:0) and multi-

function pins D_IN(21:0), HOST_AD(19:0). See Table TBD.

D_OUT(3:0) are multi-function pins.

SCL I

C bus clock (5V tolerant & Schmitt trigger)

SDA I/O

C bus data (5V tolerant & Schmitt trigger)

INT_OUT O

Interrupt output (active low or high)

Host Interface

I2C_MODE I

C bus 16-bit mode selection input

When open or high, the 16-bit mode (MDIN-2xx compatible) is

selected. When low, the 8-bit mode is selected.

Table 1-3. MDIN-380 I/O Signal Descriptions

剩余141页未读，继续阅读

TangoTang

粉丝: 13
资源: 6

MDIN-3xx系列：集成HDMI发射器与VGA转换的高清视频处理器数据手册

MDIN380demo板源码

MDIN3xx_mainAPI_v0.2_26Aug2011.zip

MDIN380资料

MDIN400规格书

Mdin380芯片驱动代码.rar_JJ5_MDIN380_YY6V_Ypbpr_驱动参考代码

MDIN165_datasheet_v01_20100319.pdf

MDIN200 VGA开发手册：视频处理与驱动指南

Vue2 全家桶 + Vant 搭建大型单页面商城项目 新蜂商城前床分离版本-前端Vue 项目源码.zip

【创新未发表】基于matlab沙猫群算法SCSO-PID控制器优化【含Matlab源码 9671期】.zip

基于MySQL+Spark+Echarts+SpringBoot的豆瓣电影数据可视化项目源码+文档说明

最新资源

Vue2 全家桶 + Vant 搭建大型单页面商城项目新蜂商城前床分离版本-前端Vue 项目源码.zip