PlanAhead用户指南：掌握UCF文件编写

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"PlanAhead是一款由Xilinx公司提供的设计规划与实现工具，主要应用于 FPGA 设计流程。这份用户指南UG632(v13.1)是2011年3月1日发布的版本，旨在帮助用户掌握如何使用PlanAhead进行设计优化、约束设置以及综合布局等任务，尤其在编写UCF（用户约束文件）方面提供了详尽的指导。" PlanAhead是Xilinx开发的一款关键工具，它在FPGA设计流程中扮演着重要角色。通过整合逻辑综合、布局布线、时序分析等功能，PlanAhead允许设计师对设计进行预处理，优化逻辑资源的分配，确保设计能够满足性能和时序的要求。以下是PlanAhead的一些核心功能和使用场景： 1. **设计规划**：在开始设计之前，PlanAhead可以帮助用户评估不同FPGA器件的适配性，预测资源利用率，并进行初步的逻辑划分。 2. **约束设置**：使用UCF（User Constraints File）文件，用户可以指定设计中各部分的时序、I/O接口和其他特殊需求。通过PlanAhead，用户可以方便地创建和编辑UCF文件，确保设计在物理实现时满足这些约束。 3. **逻辑综合**：Plan Ahead支持与Xilinx的其他工具（如ISE Design Suite）协同工作，将HDL代码（如VHDL或Verilog）转换为门级网表，这一过程称为逻辑综合。 4. **布局与布线**：在综合完成后，PlanAhead可执行布局布线，将逻辑单元分配到FPGA的物理资源上，并连接这些单元，以满足设计的时序约束。 5. **时序分析**：工具会对设计进行时序分析，提供详细的报告，显示设计的时序性能，帮助用户找出可能的瓶颈并进行优化。 6. **IP集成**：PlanAhead也支持集成Xilinx的IP核，使得用户可以方便地导入和配置现成的功能模块，加速设计进程。 7. **调试与验证**：在设计实现过程中，PlanAhead提供了调试和验证功能，例如查看波形，检查逻辑状态等，帮助用户在硬件实现前发现并解决问题。使用PlanAhead，设计者不仅能得到一个高效的FPGA设计流程，还能确保设计符合特定的应用需求。然而，需要注意的是，Xilinx对文档的更新和维护具有最终决定权，可能会随时发布新的版本以修复错误或添加新特性。因此，为了获取最新的技术信息和支持，用户应定期访问Xilinx的官方网站。在实际操作中，遵循文档的指导，结合实际设计项目，深入理解并熟练运用PlanAhead的各项功能，将有助于提升FPGA设计的效率和成功率。同时，由于文档中的信息“按原样”提供，不包含任何明示或暗示的保证，用户在使用过程中应谨慎对待，以避免潜在的技术问题和责任风险。

16 www.xilinx.com PlanAhead User Guide

UG632 (v13.1) March 1, 2011

Chapter 1: Introduction

You can use the PlanAhead software as a standalone software tool, or launch it for specific

purposes from the ISE software.

The full suite of PlanAhead features is available when you launch it as a standalone tool,

and a subset of specific features is available when launched from Project Navigator; this

subset is called ISE Integration Mode.

Refer to Chapter 15, Using PlanAhead With Project Navigator, for more information about

integration with Project Navigator.

Using The PlanAhead Software

You can use the PlanAhead software for FPGA design at a variety of starting points. In

PlanAhead, you can:

• Manage

the design data flow from Register Transfer Level (RTL) development

through bitstream generation with a push button run process

• Perform RTL design and analysis using an elaborated RTL netlist

• Perform behavioral and timing simulation using the integrated Xilinx ISim tool

• Export I/O Buffer Information Specification (IBIS) models

• Customize and implement IP using the integrated CORE Generator tool

• Configure and launch multiple Synthesis and Implementation runs

• Perform I/O pin planning

• Manage constraints and perform floorplanning

• Estimate the resource utilization, timing, power consumption and perform Design

Rule Checks (DRCs)

• Debug core insertion and implementation with the integrated ChipScope debugging

tool

• Perform device configuration and file generation using the iMPACT tool

• Analyze implementation results

• Launch programming and design verification tools

Project Creation and Management

The PlanAhead software provides a variety of options for project creation and

management, as well as creation of various constraint sets for exploration purposes. Refer

to Chapter 3, Working with Projects for more information.

RTL and IP Design

The PlanAhead software RTL Design environment lets you create and manage RTL design

files. You can customize and implement IP through integration with CORE Generator. In

addition to basic source file creation and management, PlanAhead provides RTL design

elaboration enabling RTL logic exploration, an RTL Schematic Viewer, a set of RTL DRCs,

and RTL-based resource and power estimation. Chapter 5, RTL Design, contains more

information.

PlanAhead User Guide www.xilinx.com 17

UG632 (v13.1) March 1, 2011

Using The PlanAhead Software

Design Simulation

The PlanAhead software also allows you to launch Xilinx ISim to perform behavioral

simulation of HDL designs, and full timing simulation of implemented designs.

PlanAhead prepares the required simulation e

xecutables and launches the ISim Graphical

User Interface (GUI) to allow you to simulate the design, add and view signals in the

waveform viewer, examine and debug the design as needed. For more information, see:

• Chapt

er 5, RTL Design contains information about Behavioral simulation.

• Chapter 11, Analyzing Implementation Results describes the Timing simulation.

Synthesis and Implementation

The PlanAhead software includes a synthesis and implementation environment that

allows multiple synthesis and implementation attempts using different software

command options, and timing or physical constraints. The synthesis and implementation

attempts or runs can be queued to launch sequentially or simultaneously with

multi-processor machines using the Xilinx ISE synthesis and implementation software.

• Chapt

er 6, Synthesizing the Design describes how to use synthesis.

• Chapter 9, Implementing the Design describes how to use implementation.

Design Analysis and Constraints Definition

The PlanAhead software provides an environment in which you can analyze the design at

each stage of the design process. Early resource, timing and power estimations along with

DRCs enable you to experiment with various devices, constraints, as well as synthesis and

implementation options to achieve desired results. After implementation you can also

launch FPGA Editor and XPower Analyzer tools directly from PlanAhead.

These capabilities are available both before and aft

er implementation by analyzing the

synthesized netlist design or the implemented design results. For more information, see:

• Chapt

er 7, Netlist Analysis and Constraint Definition

• Chapter 11, Analyzing Implementation Results

Pin Planning

The PlanAhead software contains an I/O Planner environment that provides an interface

to analyze the design and device I/O requirements, and lets you define an I/O pinout

configuration or pinout that satisfies the requirements of both the Printed Circuit Board

(PCB) and the Field Programmable Gate Array (FPGA) designers. Chapter 8, I/O Pin

Planning contains more information about I/O pin planning,

Floorplanning

The PlanAhead software supports a floorplanning methodology that lets you constrain

critical logic to ensure shorter interconnect lengths with less delay, and to ensure more

predictable implementation results. You can floorplan a Design by creating physical block

(Pblock) locations to constrain logic placement, or by locking individual logic objects to

specific device sites. See Chapter 10, Floorplanning the Design for more information about

the floorplanning capabilities in PlanAhea

d and to obtain references to the

Floorplanning User Guide (UG633), which is available on the Xilinx website.

18 www.xilinx.com PlanAhead User Guide

UG632 (v13.1) March 1, 2011

Chapter 1: Introduction

Programming and Debugging Designs and ChipScope Integration

The PlanAhead software is integrated with the Xilinx ChipScope debugging tool, which

lets you add debugging cores to your design.

After implementation, you can access the ISE tools t

o generate bitstream files, and launch

the iMPACT and ChipScope Analyzer software tools directly from PlanAhead. See

Chapter 12, Programming and Debugging the Design for more information.

Hierarchical Design, Design Preservation, and Partial Configuration

The PlanAhead software provides some advanced hierarchical design features to support

team design, design preservation, and partial reconfiguration methodologies. See

Chapter 13, Using Hierarchical Design Techniques for more information.

The

Hierarchical Design Methodology Guide (UG748), is also available to describe the

Hierarchical Design methodological process.

Tcl Commands and Batch Scripting

The syntax of Tcl command and batch options in the PlanAhead software is described in

Chapter 14, Tcl and Batch Scripting. The

PlanAhead Tcl Commands Reference Guide (UG789),

describes the Tcl commands that the PlanAhead software generates.

Using PlanAhead with the ISE Project Navigator Environment

The PlanAhead software is integrated with the Project Navigator software tool to provide

an environment for improving your design results throughout the design flow.

Project Navigator launches PlanAhead automati

cally at four different design steps:

• Pr

e-Synthesis:

• I/O pin planning

• Post-Synthesis:

• I/O pin planning

• Floorplan Area/IO/logic

• Post-Implementation:

• Analyze Timing and Floorplan design

See Chapter 15, Using PlanAhead With Project Navigator for information about

PlanAhead in the ISE Integration mode.

Input and Output Files

The PlanAhead software accepts a variety of input files and creates a variety of output file

types and formats. See Appendix A, PlanAhead Input and Output Files for descriptions of

the input and output files.

Design Rule Checks

The PlanAhead software Design Rule Checks (DRCs) are listed in

Appendix B, PlanAhead DRCs.

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