Xilinx PlanAhead User Guide v13.1

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"PlanAhead 用户指南 (UG632 v13.1)，是Xilinx公司为用户提供的设计开发工具的使用手册，旨在帮助用户在Xilinx硬件设备上开发设计。文档包含了对PlanAhead工具的详细操作指导。" **PlanAhead工具介绍** PlanAhead是一款由Xilinx公司提供的综合设计工具，它在Xilinx的Vivado设计套件中扮演着重要的角色。此工具主要服务于FPGA（Field-Programmable Gate Array）和SoC（System on Chip）的设计者，支持设计流程的各个阶段，包括逻辑综合、布局布线、时序分析、引脚规划以及硬件调试等。 **主要内容与功能** 1. **设计综合**: PlanAhead允许用户对HDL代码（如Verilog或VHDL）进行综合，将高级语言描述转化为逻辑门级网表，以便于后续的实现过程。 2. **约束管理**: 用户可以在这一步添加时序、电源和I/O约束，以确保设计满足特定的性能指标。 3. **物理实现**: 工具会根据综合后的结果进行布局和布线，优化设计以满足时序、面积和功耗的目标。 4. **时序分析**: 提供了详细的时序报告，帮助用户了解设计的时序性能，并进行必要的优化。 5. **引脚分配**: 允许用户指定I/O引脚的分配，以满足板级接口的需求。 6. **IP集成**: 支持Xilinx的各种IP核集成，加速设计进程。 7. **硬件调试**: 提供了硬件调试功能，如ILA（Integrated Logic Analyzer）配置和波形查看，方便用户在实际硬件上调试设计。 **许可和使用条款** 使用PlanAhead用户指南时，必须遵守Xilinx的许可协议。用户只能用于开发与Xilinx硬件设备兼容的设计，未经Xilinx的书面同意，不得复制、分发、出版、下载、展示、发布或以任何方式传输文档。Xilinx不承担因使用文档而产生的任何责任，并保留在任何时候更改文档而不事先通知的权利。同时，Xilinx对于提供的技术支持或帮助不承担任何错误或更新的相关责任。 **免责声明** 文档“按原样”提供，没有任何形式的保证。Xilinx明确否认所有明示或暗示的保证，包括但不限于对适销性、特定用途适用性的保证。使用过程中可能出现的技术支持或帮助，Xilinx不对此承担任何因使用信息导致的法律责任。总结来说，PlanAhead是一个强大的设计工具，涵盖了从设计输入到硬件实现的全过程，而《PlanAhead User Guide》则是设计师不可或缺的参考资料，提供了详尽的操作指南和最佳实践，帮助用户充分利用该工具完成复杂的FPGA和SoC设计任务。

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UG632 (v13.1) March 1, 2011

Chapter 1: Introduction

You can use the PlanAhead software as a standalone software tool, or launch it for specific

purposes from the ISE software.

The full suite of PlanAhead features is available when you launch it as a standalone tool,

and a subset of specific features is available when launched from Project Navigator; this

subset is called ISE Integration Mode.

Refer to Chapter 15, Using PlanAhead With Project Navigator, for more information about

integration with Project Navigator.

Using The PlanAhead Software

You can use the PlanAhead software for FPGA design at a variety of starting points. In

PlanAhead, you can:

• Manage

the design data flow from Register Transfer Level (RTL) development

through bitstream generation with a push button run process

• Perform RTL design and analysis using an elaborated RTL netlist

• Perform behavioral and timing simulation using the integrated Xilinx ISim tool

• Export I/O Buffer Information Specification (IBIS) models

• Customize and implement IP using the integrated CORE Generator tool

• Configure and launch multiple Synthesis and Implementation runs

• Perform I/O pin planning

• Manage constraints and perform floorplanning

• Estimate the resource utilization, timing, power consumption and perform Design

Rule Checks (DRCs)

• Debug core insertion and implementation with the integrated ChipScope debugging

tool

• Perform device configuration and file generation using the iMPACT tool

• Analyze implementation results

• Launch programming and design verification tools

Project Creation and Management

The PlanAhead software provides a variety of options for project creation and

management, as well as creation of various constraint sets for exploration purposes. Refer

to Chapter 3, Working with Projects for more information.

RTL and IP Design

The PlanAhead software RTL Design environment lets you create and manage RTL design

files. You can customize and implement IP through integration with CORE Generator. In

addition to basic source file creation and management, PlanAhead provides RTL design

elaboration enabling RTL logic exploration, an RTL Schematic Viewer, a set of RTL DRCs,

and RTL-based resource and power estimation. Chapter 5, RTL Design, contains more

information.

PlanAhead User Guide www.xilinx.com 17

UG632 (v13.1) March 1, 2011

Using The PlanAhead Software

Design Simulation

The PlanAhead software also allows you to launch Xilinx ISim to perform behavioral

simulation of HDL designs, and full timing simulation of implemented designs.

PlanAhead prepares the required simulation e

xecutables and launches the ISim Graphical

User Interface (GUI) to allow you to simulate the design, add and view signals in the

waveform viewer, examine and debug the design as needed. For more information, see:

• Chapt

er 5, RTL Design contains information about Behavioral simulation.

• Chapter 11, Analyzing Implementation Results describes the Timing simulation.

Synthesis and Implementation

The PlanAhead software includes a synthesis and implementation environment that

allows multiple synthesis and implementation attempts using different software

command options, and timing or physical constraints. The synthesis and implementation

attempts or runs can be queued to launch sequentially or simultaneously with

multi-processor machines using the Xilinx ISE synthesis and implementation software.

• Chapt

er 6, Synthesizing the Design describes how to use synthesis.

• Chapter 9, Implementing the Design describes how to use implementation.

Design Analysis and Constraints Definition

The PlanAhead software provides an environment in which you can analyze the design at

each stage of the design process. Early resource, timing and power estimations along with

DRCs enable you to experiment with various devices, constraints, as well as synthesis and

implementation options to achieve desired results. After implementation you can also

launch FPGA Editor and XPower Analyzer tools directly from PlanAhead.

These capabilities are available both before and aft

er implementation by analyzing the

synthesized netlist design or the implemented design results. For more information, see:

• Chapt

er 7, Netlist Analysis and Constraint Definition

• Chapter 11, Analyzing Implementation Results

Pin Planning

The PlanAhead software contains an I/O Planner environment that provides an interface

to analyze the design and device I/O requirements, and lets you define an I/O pinout

configuration or pinout that satisfies the requirements of both the Printed Circuit Board

(PCB) and the Field Programmable Gate Array (FPGA) designers. Chapter 8, I/O Pin

Planning contains more information about I/O pin planning,

Floorplanning

The PlanAhead software supports a floorplanning methodology that lets you constrain

critical logic to ensure shorter interconnect lengths with less delay, and to ensure more

predictable implementation results. You can floorplan a Design by creating physical block

(Pblock) locations to constrain logic placement, or by locking individual logic objects to

specific device sites. See Chapter 10, Floorplanning the Design for more information about

the floorplanning capabilities in PlanAhea

d and to obtain references to the

Floorplanning User Guide (UG633), which is available on the Xilinx website.

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UG632 (v13.1) March 1, 2011

Chapter 1: Introduction

Programming and Debugging Designs and ChipScope Integration

The PlanAhead software is integrated with the Xilinx ChipScope debugging tool, which

lets you add debugging cores to your design.

After implementation, you can access the ISE tools t

o generate bitstream files, and launch

the iMPACT and ChipScope Analyzer software tools directly from PlanAhead. See

Chapter 12, Programming and Debugging the Design for more information.

Hierarchical Design, Design Preservation, and Partial Configuration

The PlanAhead software provides some advanced hierarchical design features to support

team design, design preservation, and partial reconfiguration methodologies. See

Chapter 13, Using Hierarchical Design Techniques for more information.

The

Hierarchical Design Methodology Guide (UG748), is also available to describe the

Hierarchical Design methodological process.

Tcl Commands and Batch Scripting

The syntax of Tcl command and batch options in the PlanAhead software is described in

Chapter 14, Tcl and Batch Scripting. The

PlanAhead Tcl Commands Reference Guide (UG789),

describes the Tcl commands that the PlanAhead software generates.

Using PlanAhead with the ISE Project Navigator Environment

The PlanAhead software is integrated with the Project Navigator software tool to provide

an environment for improving your design results throughout the design flow.

Project Navigator launches PlanAhead automati

cally at four different design steps:

• Pr

e-Synthesis:

• I/O pin planning

• Post-Synthesis:

• I/O pin planning

• Floorplan Area/IO/logic

• Post-Implementation:

• Analyze Timing and Floorplan design

See Chapter 15, Using PlanAhead With Project Navigator for information about

PlanAhead in the ISE Integration mode.

Input and Output Files

The PlanAhead software accepts a variety of input files and creates a variety of output file

types and formats. See Appendix A, PlanAhead Input and Output Files for descriptions of

the input and output files.

Design Rule Checks

The PlanAhead software Design Rule Checks (DRCs) are listed in

Appendix B, PlanAhead DRCs.

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Xilinx PlanAhead User Guide v13.1

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