Spartan-6 FPGA封装与引脚配置规范

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"Spartan-6 FPGA Packaging and Pinouts Specification.pdf 是Xilinx公司发布的一份详细说明文档，涵盖了Spartan-6 FPGA的封装和引脚配置信息。这份文档适用于使用Xilinx Spartan-6 FPGA进行硬件设计开发的用户，旨在提供关于芯片封装、引脚布局以及相关规格的关键信息。" 在Spartan-6 FPGA的封装和引脚配置规范中，主要包含以下几个关键知识点： 1. **Spartan-6 FPGA系列**：Spartan-6是Xilinx公司的一款FPGA（Field-Programmable Gate Array）产品线，主要用于低成本、高性能的应用场景。它提供了各种规模的逻辑单元、I/O引脚、嵌入式存储器和专用功能块，如乘法器、数字信号处理模块等。 2. **封装类型**：Spartan-6 FPGA有多种封装形式，例如BGA（Ball Grid Array）、FBGA（Fine Pitch Ball Grid Array）等，每种封装类型有不同的引脚数量和布局，以适应不同应用的需求。封装的选择会直接影响到PCB设计的复杂性和成本。 3. **引脚配置**：文档详细列出了每个封装下的引脚分配，包括电源、地线、输入/输出接口、时钟、配置引脚、JTAG调试引脚等。理解这些引脚的功能和连接方式对于正确连接FPGA与外部电路至关重要。 4. **电气特性**：文档还会提供各引脚的电气特性，如电压等级、驱动能力、输入电容等，这些参数对于确保电路的稳定性和兼容性非常重要。 5. **热性能**：Spartan-6 FPGA的封装设计也会考虑到散热问题，用户需要根据功耗和环境条件选择合适的封装以满足热管理要求。 6. **使用限制和注意事项**：文档强调了对文档的使用和分发有严格的限制，未经Xilinx许可，不得复制、分发或以任何形式公开。同时，Xilinx不对因使用该文档产生的任何问题承担法律责任，并保留随时更改文档内容而不事先通知的权利。 7. **技术支持和更新**：尽管Xilinx不承诺对文档中的错误进行修正，也不对技术支持或协助中的任何问题负责，但用户通常可以通过Xilinx官网获取最新的技术更新和纠正信息。 "Spartan-6 FPGA Packaging and Pinouts Specification.pdf"是设计者在使用Xilinx Spartan-6 FPGA进行硬件设计时不可或缺的参考材料，它提供了详细的设计指导和工程实践中的关键信息。

16 www.xilinx.com Spartan-6 FPGA Packaging

UG385 (v1.3) October 12, 2010

Chapter 1: Packaging Overview

Pin Definitions

Table 1-6 lists the pin definitions used in Spartan-6 FPGA packages. Further details on pin

functionality is available in the device user guides:

http://www.xilinx.com/support/documentation/spartan-6.htm

Table 1-6: Spartan-6 FPGA Pin Definitions

Pin Name Direction Description

User I/O Pins

IO_LXXY_#

Input/

Output

All user I/O pins are capable of differential signaling and can implement

pairs. Each user I/O is labeled IO_LXXY_#, where:

IO indicates a user I/O pin.

LXXY indicates a differential pair, with XX a unique pair in the bank

and Y = [P|N] for the positive/negative sides of the differential pair.

# indicates the bank number.

Multi-Function Pins

IO_LXXY_ZZZ_#

Multi-function pins are labelled IO_LXXY_ZZZ_#, where ZZZ

represents one or more of the following functions in addition to being

general purpose user I/O. When not used for their special function,

these pins can be user I/O.

Input/

Output

(during readback)

In SelectMAP/BPI modes, D0 through D15 are configuration data pins.

During slave SelectMAP readback, the pins become outputs when

RDWR_B = 1. These pins become user I/Os after configuration, unless

the SelectMAP port is retained.

D0_DIN_MISO_MISO1

Input

In Parallel (SelectMAP and BPI) modes, D0 is the LSB of the data bus.

In Bit-serial modes, DIN is the single-data input.

In SPI mode, MISO is the Master Input/Slave Output.

In SPI x2 or x4 modes, MISO1 is the second bit of the SPI bus.

D1_MISO2,

D2_MISO3

Input

In Parallel modes, D1 and D2 are lower-order bits of the data bus. In SPI

x4 mode, MISO2 and MISO3 are two MSBs of the SPI bus.

Output

Address A0–A25 BPI address output. These pins become user I/O after

configuration.

AWAKE

Output

Status output pin for the power-saving Suspend mode. SUSPEND is a

dedicated pin and AWAKE is a multi-function pin. Unless Suspend

mode is enabled in the application, AWAKE is available as user I/O.

MOSI_CSI_B_MISO0

Input/

Output

In SPI modes, Master Output/Slave Input (MOSI) connects from the

FPGA to the SPI flash slave data input to send read commands and

starting addresses. In SelectMAP mode, CSI_B is the active-low chip-

select signal.

In SPI x2 or x4 modes, MISO0 is the first bit of the SPI bus.

FCS_B Output BPI flash chip select.

FOE_B Output BPI flash output enable.

FWE_B Output BPI flash write enable.

LDC Output Low during configuration in BPI mode.

Spartan-6 FPGA Packaging www.xilinx.com 17

UG385 (v1.3) October 12, 2010

Pin Definitions

HDC Output High during configuration in BPI mode.

CSO_B

Output

In Parallel modes, parallel daisy-chain chip select. In SPI mode, SPI flash

chip select.

IRDY1/2,

TRDY1/2

Output

Used with LogiCORE IP for PCI designs. An instantiation of the Xilinx

core requires the use of either IRDY1 and TRDY1 or IRDY2 and TRDY2.

See the core documentation for more details. These pins are available as

user I/O when not being used for PCI designs.

DOUT_BUSY

Output

In SelectMAP mode, BUSY indicates the device status.

In Bit-serial modes, DOUT gives configuration data to down-stream

devices in a daisy chain.

RDWR_B_VREF

Input

In SelectMAP mode, this is the active-low write-enable signal. After

configuration and if needed, RDWR_B can become a V

REF

in bank 2.

HSWAPEN Input When Low, enables I/O pullups before and during configuration.

INIT_B

Bidirectional

(open-drain)

When Low, this pin indicates that the configuration memory is being

cleared. When held Low, the start of configuration is delayed. During

configuration, a Low on this output indicates that a configuration data

error has occurred. Can be used after configuration (optional) to indicate

POST_CRC status.

SCPn

Input

Suspend control pins SCP0-SCP7. Used for SUSPEND multi-pin wake-

up feature.

CMPMOSI,

CMPMISO,

CMPCLK

N/A

Reserved for future use. Use these pins as general-purpose I/O.

M0, M1

Input

Configuration mode selection. M0 = Parallel (Low) or Serial (High).

M1 = Master (Low) or Slave (High).

CCLK Input/

Output

Configuration clock. Output in Master mode or input in Slave mode.

USERCCLK Input Optional user configuration clock input in Master modes.

GCLK

Input

These clock pins connect to global clock buffers. These pins become

regular user I/Os when not needed for clocks.

VREF_#

N/A

These are input threshold voltage pins. They become user I/Os when an

external threshold voltage is not needed (per bank). When used as a

reference voltage within a bank, all V

REF

pins within that bank must be

connected.

Multi-Function Memory Controller Pins

(1)

M#DQn Input/

Output

Memory controller data D[0:15] in bank #.

M#LDQS Input/

Output

Memory controller lower data strobe in bank #.

M#LDQSN Input/

Output

Memory controller lower data strobe N in bank #.

Table 1-6: Spartan-6 FPGA Pin Definitions (Cont’d)

Pin Name Direction Description

20 www.xilinx.com Spartan-6 FPGA Packaging

UG385 (v1.3) October 12, 2010

Chapter 1: Packaging Overview

Spartan-6 FPGA Banks

Bank designations at the end of each pin name indicate the bank number for that pin. There

are both I/O banks and GTP transceiver banks in the Spartan-6 family.

Spartan-6 FPGA I/O Banks

Each Spartan-6 device contains either four or six I/O banks depending on device size and

package. Each bank varies in the number of available and bonded I/O, with as few as 18

and as many as 114 I/O available in one bank.

• XC6SLX45/XC6SLX45T and smaller and all devices in the CSG484 and FG(G)484

packages have four I/O banks, one on each side of the device.

• XC6SLX75/XC6SLX75T and larger in the FG(G)676 and FG(G)900 packages have two

I/O banks on the left and right sides for a total of six I/O banks.

Spartan-6 LXT FPGA GTP Transceiver Banks

There are from one to four GTPA1_DUAL tiles in each Spartan-6 LXT device. Each

GTPA1_DUAL tile has its own power supplies and bank designation. GTP transceiver

banks 101 and 123 are embedded in I/O bank 0, and GTP transceiver banks 245 and 267 are

embedded in I/O bank 2.

GTP Transceiver Pins (GTPA1_DUAL Primitive)

(3)

MGTAVCC N/A Power-supply pin for transceiver mixed-signal circuitry.

MGTAVTTTX,

MGTAVTTRX

N/A

Power-supply pin for TX and RX circuitry.

MGTAVTTRCAL N/A Power-supply pin for the resistor calibration circuit.

MGTAVCCPLL0

MGTAVCCPLL1

N/A

Power-supply pin for PLL.

MGTREFCLK0/1P Input Positive differential reference clock.

MGTREFCLK0/1N Input Negative differential reference clock.

MGTRREF Input Precision reference resistor pin for internal calibration termination.

MGTRXP[0:1] Input Positive differential receive port.

MGTRXN[0:1] Input Negative differential receive port.

MGTTXP[0:1] Output Positive differential transmit port.

MGTTXN[0:1] Output Negative differential transmit port.

Notes:

1. For further information, see UG388: Spartan-6 FPGA Memory Controller User Guide.

2. Dedicated pins without a bank number (JTAG and SUSPEND) are powered by V

CCAUX

3. For further information, see UG386

: Spartan-6 FPGA GTP Transceivers User Guide.

Table 1-6: Spartan-6 FPGA Pin Definitions (Cont’d)

Pin Name Direction Description

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