"Renesas RH850F1KM-S4用户手册信息更新及变更通知"

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The Renesas RH850F1KM-S4 is a powerful microcontroller in the RH850 Family, boasting advanced features and capabilities. This user's manual provides detailed information on the product specifications and functionalities at the time of publication. However, it is important to note that the information is subject to change by Renesas Electronics Corp. without notice. Users are advised to refer to the latest information available on the Renesas Electronics Corp. website to stay updated on any changes or updates regarding the RH850F1KM-S4. The Renesas RH850F1KM-S4 microcontroller offers a wide range of applications and is known for its high performance and reliability. With the capabilities of the RH850 Family, this microcontroller is suitable for various industries and projects that require advanced processing power and efficiency. The user's manual provides comprehensive guidance and instructions on the configuration, programming, and usage of the RH850F1KM-S4 microcontroller. It covers topics such as system architecture, peripherals, memory organization, and software development tools. This information is crucial for developers and engineers looking to utilize the full potential of the RH850F1KM-S4 in their projects. In conclusion, the Renesas RH850F1KM-S4 is a top-of-the-line microcontroller with advanced features and capabilities. This user's manual serves as a valuable resource for understanding and utilizing the product to its full potential. Developers and engineers can rely on the RH850F1KM-S4 for their projects, knowing that it offers high performance, reliability, and flexibility for a wide range of applications.

2C.10.3 Port 8 (P8) .......................................................................................................................... 532

2C.10.3.1 Alternative Function ................................................................................................ 532

2C.10.3.2 Control Registers .................................................................................................... 534

2C.10.4 Port 9 (P9) .......................................................................................................................... 536

2C.10.4.1 Alternative Function ................................................................................................ 536

2C.10.4.2 Control Registers .................................................................................................... 537

2C.10.5 Port 10 (P10) ...................................................................................................................... 539

2C.10.5.1 Alternative Function ................................................................................................ 539

2C.10.5.2 Control Registers .................................................................................................... 541

2C.10.6 Port 11 (P11) ...................................................................................................................... 543

2C.10.6.1 Alternative Function ................................................................................................ 543

2C.10.6.2 Control Registers .................................................................................................... 544

2C.10.7 Analog Port 0 (AP0) ........................................................................................................... 545

2C.10.7.1 Alternative Function ................................................................................................ 545

2C.10.7.2 Control Registers .................................................................................................... 546

2C.11 Port (Special I/O) Function Overview ........................................................................................... 547

2C.11.1 Special I/O after Reset ....................................................................................................... 547

2C.11.1.1 P8_6: RESETOUT ................................................................................................ 547

2C.11.1.2 JP0_0 to JP0_5: Debug Interface ........................................................................... 550

2C.11.1.3 FPDR(JP0_0), FPDT(JP0_1), FPCK(JP0_2): Flash Programmer ......................... 550

2C.11.1.4 Mode Pins ............................................................................................................... 550

2C.11.2 A/D Input Alternative I/O .................................................................................................... 551

2C.11.3 Special I/O Control ............................................................................................................. 552

2C.11.3.1 Direct I/O Control (PIPC) ........................................................................................ 552

2C.11.3.2 Input Buffer Control (PISn/JPIS0, JPISA0) ............................................................. 553

2C.11.3.3 Output Buffer Control (PDSC) ................................................................................ 555

2C.12 Noise Filter & Edge/Level Detector .............................................................................................. 557

2C.12.1 Port Filter Assignment ........................................................................................................ 557

2C.12.1.1 Input Pins that Incorporate Analog Filter Type A .................................................... 557

2C.12.1.2 Input Pins that Incorporate Analog Filter Type B .................................................... 558

2C.12.1.3 Input Pins that Incorporate Analog Filter Type C .................................................... 559

2C.12.1.4 Input Pins that Incorporate Digital Filter Type D ..................................................... 560

2C.12.1.5 Input Pins that Incorporate Digital Filter Type E ..................................................... 561

2C.12.2 Clock Supply for Port Filters .............................................................................................. 563

2C.13 Description of Port Noise Filter & Edge/Level Detection .............................................................. 564

2C.13.1 Overview ............................................................................................................................ 564

2C.13.1.1 Analog Filter Types ................................................................................................. 564

2C.13.1.2 Digital Filter Types .................................................................................................. 564

2C.13.2 Analog Filters ..................................................................................................................... 565

2C.13.2.1 Analog Filter Characteristic ..................................................................................... 565

2C.13.2.2 Analog Filter Control Registers ............................................................................... 565

2C.13.2.3 Analog Filter in Standby Mode ................................................................................ 565

2C.13.3 Digital Filters ...................................................................................................................... 568

2C.13.3.1 Digital Filter Characteristic ...................................................................................... 568

2C.13.3.2 Digital Filter Groups ................................................................................................ 569

2C.13.3.3 Digital Filters in Standby Mode ............................................................................... 569

2C.13.3.4 Digital Filter Control Registers ................................................................................ 570

2C.13.4 Filter Control Registers ...................................................................................................... 571

2C.13.4.1 FCLA0CTLm_<name> — Filter Control Register ................................................... 572

2C.13.4.2 DNFA<name>CTL — Digital Noise Elimination Control Register .......................... 573

2C.13.4.3 DNFA<name>EN — Digital Noise Elimination Enable Register ............................ 574

2C.13.4.4 DNFA<name>ENH — Digital Noise Elimination Enable H Register ...................... 575

2C.13.4.5 DNFA<name>ENL — Digital Noise Elimination Enable L Register ....................... 575

Section 3A CPU System of RH850/F1KH-D8 .............................................................. 576

3A.1 Overview ....................................................................................................................................... 576

3A.1.1 Block Configuration ............................................................................................................ 576

3A.2 CPU .............................................................................................................................................. 579

3A.2.1 Core Functions ................................................................................................................... 579

3A.2.1.1 Features .................................................................................................................. 579

3A.2.1.2 Register Set ............................................................................................................ 580

3A.2.1.3 Instruction ............................................................................................................... 617

3A.2.2 Buffers for Code Flash ....................................................................................................... 618

3A.2.2.1 Features .................................................................................................................. 618

3A.2.2.2 Function of Buffers .................................................................................................. 618

3A.2.2.3 Registers for Buffer Control .................................................................................... 619

3A.2.3 Inter-Processor Interrupts .................................................................................................. 620

3A.2.3.1 Inter-Processor Interrupt Control Registers ............................................................ 620

3A.2.4 Reliability Functions ........................................................................................................... 622

3A.2.4.1 PE Guard Function (PEG) ...................................................................................... 622

3A.2.4.2 PE’s Internal Peripheral Device Protection Function (IPG) .................................... 628

3A.2.4.3 System Error Generator Function (SEG) ................................................................ 635

3A.3 Inter-CPU Functions ..................................................................................................................... 640

3A.3.1 Processor Element Identifier .............................................................................................. 640

3A.3.2 Inter-Processor Interrupt Function ..................................................................................... 640

3A.3.3 Exclusive Control ............................................................................................................... 640

3A.3.3.1 Exclusive Control Register (G0MEVm; m = 0 to 31) .............................................. 640

3A.3.3.2 Operation of the LDL.W and STC.W Instructions ................................................... 642

3A.4 CPU2 Boot Up Operation ............................................................................................................. 643

3A.5 Notes............................................................................................................................................. 644

3A.5.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution . 644

3A.5.2 Ensure Coherency after Rewriting the Code Flash ........................................................... 645

3A.5.3 Access to Registers by Using Bit-Manipulation Instructions .............................................. 645

3A.5.4 Caution of Prefetching ....................................................................................................... 645

3A.5.5 Overwriting Context upon Acceptance of Multiple Exceptions .......................................... 645

Section 3BC CPU System of RH850/F1KM ......................................................................... 646

3BC.1 Overview ....................................................................................................................................... 646

3BC.1.1 Block Configuration ............................................................................................................ 646

3BC.2 CPU .............................................................................................................................................. 649

3BC.2.1 Core Functions ................................................................................................................... 649

3BC.2.1.1 Features .................................................................................................................. 649

3BC.2.1.2 Register Set ............................................................................................................ 650

3BC.2.1.3 Instruction ............................................................................................................... 687

3BC.2.2 Buffers for Code Flash ....................................................................................................... 688

3BC.2.2.1 Features .................................................................................................................. 688

3BC.2.2.2 Function of Buffers .................................................................................................. 688

3BC.2.2.3 Registers for Buffer Control .................................................................................... 689

3BC.2.3 Reliability Functions ........................................................................................................... 690

3BC.2.3.1 PE Guard Function (PEG) ...................................................................................... 690

3BC.2.3.2 PE’s Internal Peripheral Device Protection Function (IPG) .................................... 696

3BC.2.3.3 System Error Generator Function (SEG) ................................................................ 703

3BC.3 Notes............................................................................................................................................. 709

3BC.3.1 Synchronization of Store Instruction Completion and Subsequent Instruction Execution . 709

3BC.3.2 Ensure Coherency after Rewriting the Code Flash ........................................................... 710

3BC.3.3 Access to Registers by Using Bit-Manipulation Instructions .............................................. 710

3BC.3.4 Caution of Prefetching ....................................................................................................... 710

3BC.3.5 Overwriting Context upon Acceptance of Multiple Exceptions .......................................... 710

Section 4A Address Space of RH850/F1KH-D8 ........................................................... 711

4A.1 Address Space ............................................................................................................................. 711

4A.2 Address Space Viewed from Each Bus Master ............................................................................ 714

4A.2.1 Space in which Instructions can be Fetched ..................................................................... 714

4A.2.2 Data Space Accessible by CPU1 ....................................................................................... 714

4A.2.3 Data Space Accessible by CPU2 ....................................................................................... 714

4A.2.4 Data Space Accessible by DMA ........................................................................................ 714

4A.2.5 Data Space Accessible by Flexray .................................................................................... 714

4A.2.6 Data Space Accessible by ETNB ....................................................................................... 714

4A.2.7 Data Space Accessible by Each Bus Master ..................................................................... 715

4A.3 Peripheral I/O Address Map ......................................................................................................... 717

Section 4B Address Space of RH850/F1KM-S4, RH850/F1KM-S2 ............................. 725

4B.1 Address Space ............................................................................................................................. 725

4B.2 Address Space Viewed from Each Bus Master ............................................................................ 734

4B.2.1 Space in which Instructions can be Fetched ..................................................................... 734

4B.2.2 Data Space Accessible by CPU ......................................................................................... 734

4B.2.3 Data Space Accessible by DMA ........................................................................................ 734

4B.2.4 Data Space Accessible by Flexray .................................................................................... 734

4B.2.5 Data Space Accessible by ETNB ....................................................................................... 734

4B.2.6 Data Space Accessible by Each Bus Master ..................................................................... 735

4B.3 Peripheral I/O Address Map ......................................................................................................... 737

Section 4C Address Space of RH850/F1KM-S1 .......................................................... 751

4C.1 Address Space ............................................................................................................................. 751

4C.2 Address Space Viewed from Each Bus Master ............................................................................ 753

4C.2.1 Space in which Instructions can be Fetched ..................................................................... 753

4C.2.2 Data Space Accessible by CPU ......................................................................................... 753

4C.2.3 Data Space Accessible by Each Bus Master ..................................................................... 753

4C.3 Peripheral I/O Address Map ......................................................................................................... 754

Section 5 Write-Protected Registers ............................................................................... 760

5.1 Overview ....................................................................................................................................... 760

5.1.1 Functional Overview .......................................................................................................... 760

5.1.2 Writing Procedure to Write-Protected Registers ................................................................ 760

5.1.3 Interrupt during Write Protection Unlock ............................................................................ 761

5.1.4 Emulation Break during Write Protection Unlock Sequence ............................................. 762

5.1.5 Write-Protection Target Registers ...................................................................................... 762

5.2 Registers ....................................................................................................................................... 772

5.2.1 List of Registers ................................................................................................................. 772

5.2.2 Details of Control Protection Cluster Registers ................................................................. 779

5.2.2.1 PROTCMDn — Protection Command Register ...................................................... 779

5.2.2.2 PROTSn — Protection Status Register .................................................................. 780

5.2.3 Details of Clock Monitor Control and Test Protection Cluster Registers ........................... 781

5.2.3.1 CLMAnPCMD — CLMAn Protection Command Register ...................................... 781

5.2.3.2 CLMAnPS — CLMAn Protection Status Register .................................................. 782

5.2.3.3 PROTCMDCLMA — Clock Monitor Test Protection Command Register .............. 783

5.2.3.4 PROTSCLMA — Clock Monitor Test Protection Status Register ........................... 784

5.2.4 Details of Core Voltage Monitor Protection Cluster Registers ........................................... 785

5.2.4.1 PROTCMDCVM — Core Voltage Monitor Protection Command Register ............ 785

5.2.4.2 PROTSCVM — Core Voltage Monitor Protection Status Register ......................... 786

5.2.5 Details of Port Protection Cluster Registers ...................................................................... 787

5.2.5.1 PPCMDn — Port Protection Command Register ................................................... 787

5.2.5.2 PPROTSn — Port Protection Status Register ........................................................ 788

5.2.6 Details of Self-Programming Protection Cluster Registers ................................................ 789

5.2.6.1 FLMDPCMD — FLMD Protection Command Register ........................................... 789

5.2.6.2 FLMDPS — FLMD Protection Error Status Register .............................................. 790

Section 6 Operating Mode .............................................................................................. 791

Section 7A Exception/Interrupts of RH850/F1KH-D8 ................................................... 792

7A.1 Features of RH850/F1KH Exception/Interrupts ............................................................................ 792

7A.2 Interrupt Sources .......................................................................................................................... 795

7A.2.1 Interrupt Sources ................................................................................................................ 795

7A.2.1.1 FE Level Non-Maskable Interrupts ......................................................................... 795

7A.2.1.2 FE Level Maskable Interrupts ................................................................................. 795

7A.2.1.3 EI Level Maskable Interrupts .................................................................................. 797

7A.2.2 FE Level Non-Maskable Interrupt Sources ........................................................................ 809

7A.2.2.1 List of Registers ...................................................................................................... 809

7A.2.2.2 WDTNMIF — FENMI Factor Register .................................................................... 809

7A.2.2.3 WDTNMIFC — WDTNMI Factor Clear Register .................................................... 810

7A.2.3 FE Level Maskable Interrupt Sources ................................................................................ 811

7A.2.3.1 List of Registers ...................................................................................................... 811

7A.2.3.2 FEINTF — FEINT Factor Register .......................................................................... 811

7A.2.3.3 FEINTFMSK — FEINT Factor Mask Register ........................................................ 814

7A.2.3.4 FEINTFC — FEINT Factor Clear Register ............................................................. 817

7A.3 Edge/Level Detection.................................................................................................................... 820

7A.4 Interrupt Controller Control Registers ........................................................................................... 821

7A.4.1 List of Registers ................................................................................................................. 821

7A.4.2 ICxxx — EI Level Interrupt Control Registers .................................................................... 822

7A.4.3 IMRm — EI Level Interrupt Mask Registers (m = 0 to 11) ................................................. 824

7A.4.4 IBDxxx — EI Level Interrupt Binding Registers ................................................................. 825

7A.4.5 FNC — FE Level NMI Status Register............................................................................... 835

7A.4.6 FIC — FE Level Maskable Interrupt Status Register ......................................................... 836

7A.5 EI Level Maskable Interrupt Select Register ................................................................................ 837

7A.5.1 List of Registers ................................................................................................................. 837

7A.5.2 SELB_INTC1 — INTC1 Interrupt Select Register ............................................................. 838

7A.6 Interrupt Function System Registers ............................................................................................ 840

7A.6.1 FPIPR — FPI Exception Interrupt Priority .......................................................................... 840

7A.6.2 ISPR — Priority of Interrupt being Serviced ...................................................................... 840

7A.6.3 PMR — Interrupt Priority Masking ..................................................................................... 840

7A.6.4 ICSR — Interrupt Control Status ........................................................................................ 840

7A.6.5 INTCFG — Interrupt Function Setting ............................................................................... 840

7A.7 Operation when Acknowledging an Interrupt ............................................................................... 841

7A.7.1 Exception Source Codes for Different Types of SYSERR Exceptions .............................. 843

7A.8 Return from Interrupts ................................................................................................................... 844

7A.9 Interrupt Operation ........................................................................................................................ 845

7A.9.1 Interrupt Mask Function of EI Level Maskable Interrupt (EIINT) ....................................... 845

7A.9.2 Interrupt Priority Level Judgment ....................................................................................... 845

7A.9.2.1 Comparison with the Priority Level of the Interrupt Currently being Handled......... 846

7A.9.2.2 Masking through Priority Mask Register (PMR) ..................................................... 846

7A.9.2.3 The Requested Interrupt Source with the Highest Priority Level is Selected ......... 846

7A.9.2.4 Interrupt Suspended by CPU .................................................................................. 846

7A.9.3 Interrupt Request Acknowledgement Conditions and the Priority ..................................... 850

7A.9.4 Exception Priority of Interrupts and the Priority Mask ........................................................ 850

7A.9.5 Interrupt Priority Mask ........................................................................................................ 850

7A.9.6 Priority Mask Function ....................................................................................................... 850

7A.9.7 Exception Management ..................................................................................................... 850

7A.9.8 Inter-Processor Interrupts .................................................................................................. 851

7A.9.9 Broadcast Function (Broadcast Communication Function) ............................................... 851

7A.9.9.1 Example of Operation ............................................................................................. 852

7A.9.9.2 Inter-Processor Interrupt Flow ................................................................................ 853

7A.10 Exception Handler Address .......................................................................................................... 854

7A.10.1 Direct Vector Method ......................................................................................................... 855

7A.10.2 Table Reference Method ................................................................................................... 857

Section 7BC Exception/Interrupts of RH850/F1KM ............................................................. 859

7BC.1 Features of RH850/F1KM Exception/Interrupts ........................................................................... 859

7BC.2 Interrupt Sources .......................................................................................................................... 861

7BC.2.1 Interrupt Sources ................................................................................................................ 861

7BC.2.1.1 FE Level Non-Maskable Interrupts ......................................................................... 861

7BC.2.1.2 FE Level Maskable Interrupts ................................................................................. 861

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