TVP5150AM1规格书：德州仪器产品的重要更新与注意事项

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"TVP5150AM1规格书" TVP5150AM1是一款专为数字音频视频应用设计的集成电路，由德州仪器（Texas Instruments, TI）公司开发。这本数据手册是May 2004年发布的重要资料，用于提供产品的详细规格、功能和性能信息。在购买或使用前，用户应确保获取最新且完整的产品信息，因为TI保留随时对产品进行改进、优化或停止供应的权利。该产品的主要特点包括但不限于： 1. 规格说明：手册中详细列出了TVP5150AM1的各项技术参数，如工作电压、输入/输出接口、功耗等，这些都是设计和评估系统时必不可少的数据。 2. 保修政策：TI为其硬件产品提供标准保修，保证在销售时产品的性能符合当时的规格。然而，保修不覆盖应用支持或客户产品设计，这意味着用户需自行承担应用相关的技术支持需求。 3. 质量控制：TI采用测试和质量控制措施来支持其保修承诺，但并非所有产品的所有参数都经过了全面测试，可能仅满足政府要求的最低标准。 4. 注意事项：在使用TVP5150AM1时，必须遵守TI的销售条款和条件，这些可能会随着时间和市场变化而更新。因此，始终确保了解最新的购买指南和政策。 5. 版权与责任声明：在购买之前，用户应明确知晓，除非法律另有规定，否则任何产品和服务的改动、终止或限制均无需通知。 TVP5150AM1规格书是电子工程师和系统设计师在设计音频视频系统时不可或缺的参考资料，它提供了关于产品特性和性能的详细信息，以及用户在使用过程中的责任和注意事项。在实际应用中，用户应根据当前的规格和技术发展，结合自己的项目需求来评估是否适合使用这款芯片。

2−1

2 Functional Description

2.1 Analog Front End

The TVP5150A decoder has an analog input channel that accepts two video inputs, which are ac-coupled. The

decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most

input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device

is 75 Ω. Please refer to the applications diagram in Figure 5−1 for the recommended configuration. The two analog

input ports can be connected as follows:

• Two selectable composite video inputs or

• One S-video input

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.

The programmable gain amplifier (PGA) and the AGC circuit work together to make sure that the input signal is

amplified sufficiently to ensure the proper input range for the ADC.

The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes from

the PLL.

2.2 Composite Processing Block Diagram

The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space. Figure 2−1

explains the basic architecture of this processing block.

Figure 2−1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5150A decoder. The

composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference

signals Cb and Cr. Cb and Cr are then low-pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk.

An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature modulator

and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue, saturation, and

sharpness (using the peaking filter) are programmable via I

The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.

2.3 Adaptive Comb Filtering

The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the

luma path, then chroma notch filters are used. TI’s patented adaptive 4-line comb filter algorithm reduces artifacts

such as hanging dots at color boundaries and detects and properly handles false colors in high frequency luminance

images such as a multiburst pattern or circle pattern.

2.4 Color Low-Pass Filter

In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of

video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr

signals.

Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image.

Please refer to Section 2.20.25, Chrominance Control #2 Register, for the response of these filters. The filters have

three options that allow three different frequency responses based on the color frequency characteristics of the input

video.

2−4

At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the

lookup table (see Section 2.20.58). This is done through port address C3h. Each read from or write to this address

will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers

(D0h−FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both

writing and reading. Full field mode must also be disabled.

Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.

Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h−AFh, both of which

are available through the I

C port.

2.9 VBI FIFO and Ancillary Data in Video Stream

Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during

the horizontal blanking period following the line from which the data was retrieved. Table 2−2 shows the header format

and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into

the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC

NABTS standard.

Table 2−2. Ancillary Data Format and Sequence

BYTE

NO.

(MSB)

D6 D5 D4 D3 D2 D1 D0

(LSB)

DESCRIPTION

0 0 0 0 0 0 0 0 0

Ancillary data preamble

1 1 1 1 1 1 1 1 1

Ancillary data preamble

2 1 1 1 1 1 1 1 1

3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID)

4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID)

5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32 bit data (NN)

6 Video line # [7:0] Internal data ID0 (IDID0)

7 0 0 0 Data

error

Match

Video line # [9:8] Internal data ID1 (IDID1)

8 1. Data Data byte

word

9 2. Data Data byte

1 word

10 3. Data Data byte

11 4. Data Data byte

: : :

m−1. Data Data byte

word

m. Data Data byte

N word

NEP EP CS[5:0] Check sum

4(N+2)−1 1 0 0 0 0 0 0 0 Fill byte

EP: Even parity for D0−D5 NEP: Negated even parity

DID: 91h: Sliced data of VBI lines of first field

53h: Sliced data of line 24 to end of first field

55h: Sliced data of VBI lines of second field

97h: Sliced data of line 24 to end of second field

SDID: This field holds the data format taken from the line mode register of the corresponding line.

NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where

each Dword is 4 bytes.

IDID0: Transaction video line number [7:0]

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