CYUSB3014-BZXC赛普拉斯3014芯片规格书

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CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *U Page 10 of 54

Clocking

FX3 allows either a crystal to be connected between the XTALIN

and XTALOUT pins or an external clock to be connected at the

CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins

can be left unconnected if they are not used.

Crystal frequency supported is 19.2 MHz, while the external

clock frequencies supported are 19.2, 26, 38.4, and 52 MHz.

FX3 has an on-chip oscillator circuit that uses an external

19.2-MHz (±100 ppm) crystal (when the crystal option is used).

An appropriate load capacitance is required with a crystal. Refer

to the specification of the crystal used to determine the appro-

priate load capacitance. The FSLC[2:0] pins must be configured

appropriately to select the crystal- or clock-frequency option. The

configuration options are shown in Table 3.

Clock inputs to FX3 must meet the phase noise and jitter require-

ments specified in Table 4 on page 10.

The input clock frequency is independent of the clock and data

rate of the FX3 core or any of the device interfaces. The internal

PLL applies the appropriate clock multiply option depending on

the input frequency.

32-kHz Watchdog Timer Clock Input

FX3 includes a watchdog timer. The watchdog timer can be used to interrupt the ARM926EJ-S core, automatically wake up the FX3

in Standby mode, and reset the ARM926EJ-S core. The watchdog timer runs a 32-kHz clock, which may be optionally supplied from

an external source on a dedicated FX3 pin.

The firmware can disable the watchdog timer. Requirements for the optional 32-kHz clock input are listed in Table 5.

Table 3. Crystal/Clock Frequency Selection

FSLC[2] FSLC[1] FSLC[0]

Crystal/Clock

Frequency

0 0 0 19.2-MHz crystal

1 0 0 19.2-MHz input CLK

1 0 1 26-MHz input CLK

1 1 0 38.4-MHz input CLK

1 1 1 52-MHz input CLK

Table 4. FX3 Input Clock Specifications

Parameter Description

Specification

Units

Min Max

Phase noise

100-Hz offset – –75

1-kHz offset – –104

10-kHz offset – –120

100-kHz offset – –128

1-MHz offset – –130

Maximum frequency deviation – – 150 ppm

Duty cycle – 30 70

%Overshoot – – 3

Undershoot – – –3

Rise time/fall time – – 3 ns

Table 5. 32-kHz Clock Input Requirements

Parameter Min Max Units

Duty cycle 40 60 %

Frequency deviation – ±200 ppm

Rise time/fall time – 200 ns

CYUSB301X/CYUSB201X

Document Number: 001-52136 Rev. *U Page 11 of 54

Power

FX3 has the following power supply domains:

■ IO_VDDQ: This is a group of independent supply domains for

digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.

FX3 provides six independent supply domains for digital I/Os

listed as follows (see Table 7 on page 15 for details on each of

the power domain signals):

❐ VIO1: GPIF II I/O

❐ VIO2: IO2

❐ VIO3: IO3

❐ VIO4: UART-/SPI/I

❐ VIO5: I

C and JTAG (supports 1.2 V to 3.3 V)

❐ CVDDQ: This is the supply voltage for clock and reset I/O. It

should be either 1.8 V or 3.3 V based on the voltage level of

the CLKIN signal.

❐ V

: This is the supply voltage for the logic core. The nominal

supply-voltage level is 1.2 V. This supplies the core logic

circuits. The same supply must also be used for the following:

• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-

tor, and other core analog circuits

• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-

ages for the USB 3.0 interface.

■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply

for the USB I/O and analog circuits. This supply powers the

USB transceiver through FX3's internal voltage regulator.

VBATT is internally regulated to 3.3 V.

Power Modes

FX3 supports the following power modes:

■ Normal mode: This is the full-functional operating mode. The

internal CPU clock and the internal PLLs are enabled in this

mode.

❐ Normal operating power consumption does not exceed the

sum of I

Core max and I

USB max (see Table 7 on page

15 for current consumption specifications).

❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be

turned off when the corresponding interface is not in use.

VIO1 cannot be turned off at any time if the GPIF II interface

is used in the application.

■ Low-power modes (see Table 6 on page 11):

❐ Suspend mode with USB 3.0 PHY enabled (L1)

❐ Suspend mode with USB 3.0 PHY disabled (L2)

❐ Standby mode (L3)

❐ Core power-down mode (L4)

Table 6. Entry and Exit Methods for Low-Power Modes

Low-Power Mode Characteristics Methods of Entry Methods of Exit

Suspend Mode with

USB 3.0 PHY

Enabled (L1)

■ The power consumption in this mode does

not exceed ISB

■ USB 3.0 PHY is enabled and is in U3 mode

(one of the suspend modes defined by the

USB 3.0 specification). This one block

alone is operational with its internal clock

while all other clocks are shut down

■ All I/Os maintain their previous state

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ The states of the configuration registers,

buffer memory, and all internal RAM are

maintained

■ All transactions must be completed before

FX3 enters Suspend mode (state of

outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion) because

the program counter does not reset

■ Firmware executing on

ARM926EJ-S core can put FX3 into

suspend mode. For example, on

USB suspend condition, firmware

may decide to put FX3 into suspend

mode

■ External Processor, through the use

of mailbox registers, can put FX3 into

suspend mode

■ D+ transitioning to low

or high

■ D- transitioning to low

or high

■ Impedance change on

OTG_ID pin

■ Resume condition on

SSRX±

■ Detection of VBUS

■ Level detect on

UART_CTS

(programmable

polarity)

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

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