eMMC 5.0标准：JESD84-B50：移动设备的高性能存储解决方案

需积分: 9 4 浏览量更新于2024-07-16 收藏 9.33MB PDF 举报

eMMC5.0是嵌入式多媒体卡（Embedded Multi-Media Card，e•MMC）的第五代电气标准，由JEDEC（固态技术协会）制定，旨在满足移动设备对高性能和低功耗的需求。eMMC是一种专门设计用于存储代码和数据的可管理内存，它融合了大容量数据传输的高吞吐量能力以及代码使用中常见小随机数据的性能优化。在eMMC5.0规范中，JESD84-B50是对前一版本JESD84-B451的修订，发布于2012年6月，更新于2013年9月。JEDEC通过其董事会和法律团队对这些标准进行了严格的审查和批准，确保它们能够消除制造商与消费者之间的误解，促进产品互换性和性能提升，并帮助消费者快速选择和获取最适合的非JEDEC成员使用的设备，无论是在国内还是国际应用。 eMMC5.0的核心特性包括： 1. **性能增强**：针对移动设备的特点，提供高效的数据处理能力，特别是在处理小块随机数据时，如代码执行时所需的频繁读取操作。 2. **高速传输**：为了支持大容量的数据传输，eMMC5.0采用优化的接口设计，使得数据读写速度大大提高，这对于现代智能手机、平板电脑等设备中的应用程序和媒体存储至关重要。 3. **安全性**：考虑到移动设备的安全需求，eMMC5.0包含多项安全特性，如加密技术、数据保护措施和权限管理，以防止未经授权的访问和数据泄露。 4. **兼容性与标准化**：作为JEDEC标准的一部分，eMMC5.0确保了与先前版本的兼容性，同时也鼓励业界遵循统一的标准，以促进设备间的互操作性和供应链的效率。 5. **法律责任声明**：JEDEC在采纳标准时，不会因可能涉及专利、材料或工艺而承担责任，但不意味着对此类问题的担保，这表明用户在使用eMMC5.0时应自行了解相关知识产权情况。 eMMC5.0是一个高度集成且成熟的存储解决方案，它不仅提供了高效的存储性能，还注重了设备的便携性和安全性，对于推动移动设备市场的发展起到了关键作用。对于任何开发移动设备或考虑升级现有系统的人来说，理解和掌握eMMC5.0标准至关重要。

JEDEC Standard No. 84-B50

-xii-

Contents (cont'd)

Page

TABLES

Table 1 e•MMC Voltage Modes ........................................................................................................................... 4

Table 2 e•MMC interface ..................................................................................................................................... 7

Table 3 e•MMC registers ...................................................................................................................................... 8

Table 4 Bus Speed Modes .................................................................................................................................. 15

Table 5 Bus modes overview .............................................................................................................................. 18

Table 6 EXT_CSD access mode ......................................................................................................................... 41

Table 7 Bus testing pattern ................................................................................................................................. 45

Table 8 1-bit bus testing pattern .......................................................................................................................... 45

Table 9 4-bit bus testing pattern .......................................................................................................................... 46

Table 10 8-bit bus testing pattern .......................................................................................................................... 46

Table 11 Erase command (CMD38) Valid arguments .......................................................................................... 55

Table 12 Erase command (CMD38) Valid arguments .......................................................................................... 59

Table 13 Write Protection Hierarchy (when disable bits are clear) ...................................................................... 62

Table 14 Write Protection Types (when disable bits are clear) ............................................................................ 62

Table 15 Security Protocol Information................................................................................................................ 64

Table 16 Lock Device data structure .................................................................................................................... 68

Table 17 Data Frame Files for RPMB .................................................................................................................. 74

Table 18 RPMB Request/Response Message Types ............................................................................................ 74

Table 19 RPMB Operation Results data structure ................................................................................................ 75

Table 20 RPMB Operation Results ....................................................................................................................... 75

Table 21 MAC Example ....................................................................................................................................... 77

Table 22 Authentication Key Data Packet ............................................................................................................ 78

Table 23 Result Register Read Request Packet .................................................................................................... 79

Table 24 Response for Key Programming Result Request ................................................................................... 79

Table 25 Counter Read Request Packet ................................................................................................................ 80

Table 26 Counter Value Response ........................................................................................................................ 80

Table 27 Program Data Packet ............................................................................................................................. 81

Table 28 Result Register Read Request Packet .................................................................................................... 82

Table 29 Response for Data Programming Result Request .................................................................................. 82

Table 30 Data Read Request Initiation Packet ...................................................................................................... 83

Table 31 Read Data Packet ................................................................................................................................... 83

Table 32 Interruptible commands ......................................................................................................................... 86

Table 33 Packed Command Structure ................................................................................................................... 93

Table 34 Features Cross Reference Table ............................................................................................................. 97

Table 35 eMMC internal sizes and related Units / Granularities ....................................................................... 100

Table 36 Admitted Data Sector Size, Address Mode and Reliable Write granularity ........................................ 102

Table 37 Real Time Clock Information Block Format ....................................................................................... 103

Table 38 RTC_INFO_TYPE Field Description .................................................................................................. 103

Table 39 Command Format ................................................................................................................................ 109

Table 40 Supported Device command classes (0–56) ........................................................................................ 110

Table 41 Basic commands (class 0 and class 1) ................................................................................................. 111

Table 42 Block-oriented read commands (class 2) ............................................................................................. 112

Table 43 Class 3 commands ............................................................................................................................... 112

JEDEC Standard No. 84-B50

-xiii-

Contents (cont'd)

Page

Table 44 Block-oriented write commands (class 4) ............................................................................................ 113

Table 45 Block-oriented write protection commands (class 6) ........................................................................... 114

Table 46 Erase commands (class 5) .................................................................................................................... 115

Table 47 I/O mode commands (class 9).............................................................................................................. 116

Table 48 Lock Device commands (class 7) ........................................................................................................ 116

Table 49 Application-specific commands (class 8) ............................................................................................ 116

Table 50 Security Protocols (class 10) ................................................................................................................ 117

Table 51 Device state transitions ........................................................................................................................ 118

Table 52 R1 response .......................................................................................................................................... 120

Table 53 R2 response .......................................................................................................................................... 121

Table 54 R3 Response ........................................................................................................................................ 121

Table 55 R4 response .......................................................................................................................................... 121

Table 56 R5 response .......................................................................................................................................... 121

Table 57 Device status ........................................................................................................................................ 123

Table 58 Device Status field/command - cross reference ................................................................................... 125

Table 59 Response 1 Status Bit Valid ................................................................................................................. 126

Table 60 Timing Parameters ............................................................................................................................... 138

Table 61 Timing Parameters for HS200 & HS400 mode ................................................................................... 139

Table 62 H/W reset timing parameters ............................................................................................................... 142

Table 63 OCR register definitions ...................................................................................................................... 144

Table 64 CID Fields ............................................................................................................................................ 145

Table 65 Device Types ....................................................................................................................................... 145

Table 66 Valid MDT “y” Field Values ............................................................................................................... 146

Table 67 CSD Fields ........................................................................................................................................... 148

Table 68 CSD register structure .......................................................................................................................... 149

Table 69 System specification version................................................................................................................ 149

Table 70 TAAC access-time definition .............................................................................................................. 149

Table 71 Maximum bus clock frequency definition ........................................................................................... 150

Table 72 Supported Device command classes .................................................................................................... 150

Table 73 Data block length ................................................................................................................................. 150

Table 74 DSR implementation code table .......................................................................................................... 151

Table 75 V

(min) current consumption ........................................................................................................... 152

Table 76 V

(max) current consumption .......................................................................................................... 152

Table 77 Multiplier factor for device size ........................................................................................................... 153

Table 78 R2W_FACTOR ................................................................................................................................... 154

Table 79 File formats .......................................................................................................................................... 155

Table 80 ECC type .............................................................................................................................................. 155

Table 81 CSD field command classes................................................................................................................. 156

Table 82 Extended CSD ..................................................................................................................................... 158

Table 83 EXT_SECURITY_ERR byte description ............................................................................................ 162

Table 84 Device-supported command sets ......................................................................................................... 162

Table 85 HPI features ......................................................................................................................................... 163

Table 86 Background operations support ........................................................................................................... 163

Table 87 Context Management Context Capabilities ......................................................................................... 164

JEDEC Standard No. 84-B50

-xiv-

Contents (cont'd)

Page

Table 88 Extended CSD Register Support .......................................................................................................... 164

Table 89 SUPPORTED_MODES ....................................................................................................................... 165

Table 90 FFU FEATURES ................................................................................................................................. 165

Table 91 MODE_OPERATION_CODES timeout definition ............................................................................ 165

Table 92 Device life time estimation type B value ............................................................................................. 166

Table 93 Device life time estimation type A value ............................................................................................. 167

Table 94 Pre EOL info value .............................................................................................................................. 167

Table 95 Optimal read size value ........................................................................................................................ 168

Table 96 Optimal write size value ...................................................................................................................... 168

Table 97 Optimal trim unit size value ................................................................................................................. 168

Table 98 Generic Switch Timeout Definition ..................................................................................................... 169

Table 99 Power off long switch timeout definition ............................................................................................ 169

Table 100 Background operations status .............................................................................................................. 170

Table 101 Correctly programmed sectors number ................................................................................................ 170

Table 102 Initialization Time out value ................................................................................................................ 170

Table 103 TRIM/DISCARD Time out value ........................................................................................................ 171

Table 104 SEC Feature Support ........................................................................................................................... 171

Table 105 Secure Erase time-out value................................................................................................................. 172

Table 106 Secure Erase time-out value................................................................................................................. 172

Table 107 Boot information .................................................................................................................................. 172

Table 108 Boot partition size ................................................................................................................................ 173

Table 109 Access size ........................................................................................................................................... 173

Table 110 Superpage size ..................................................................................................................................... 173

Table 111 Erase-unit size ...................................................................................................................................... 173

Table 112 Erase timeout values ............................................................................................................................ 174

Table 113 Reliable write sector count .................................................................................................................. 174

Table 114 Write protect group size ....................................................................................................................... 174

Table 115 S_C_VCC, S_C_VCCQ Sleep Current ............................................................................................... 175

Table 116 Production State Awareness timeout definition ................................................................................... 175

Table 117 Sleep/awake timeout values ................................................................................................................. 175

Table 118 Sleep Notification timeout values ........................................................................................................ 176

Table 119 R/W access performance values .......................................................................................................... 177

Table 120 Power classes ....................................................................................................................................... 178

Table 121 Partition switch timeout definition ....................................................................................................... 179

Table 122 Out-of-interrupt timeout definition ...................................................................................................... 179

Table 123 Supported Driver Strengths ................................................................................................................. 179

Table 124 Device types......................................................................................................................................... 180

Table 125 CSD register structure .......................................................................................................................... 180

Table 126 Extended CSD revisions ...................................................................................................................... 181

Table 127 Standard MMC command set revisions ............................................................................................... 181

Table 128 Power class codes ................................................................................................................................ 181

Table 129 HS_TIMING (timing and driver strength) ........................................................................................... 182

Table 130 HS_TIMING Interface values.............................................................................................................. 182

Table 131 Bus mode values .................................................................................................................................. 182

JEDEC Standard No. 84-B50

-xv-

Contents (cont'd)

Page

Table 132 Erased memory content values ............................................................................................................ 183

Table 133 Boot configuration bytes ...................................................................................................................... 183

Table 134 Boot config protection ......................................................................................................................... 184

Table 135 Boot bus configuration ......................................................................................................................... 184

Table 136 Bus Width and Timing Mode Transition ............................................................................................. 185

Table 137 ERASE_GROUP_DEF ........................................................................................................................ 186

Table 138 BOOT area Partitions write protection ................................................................................................ 187

Table 139 User area write protection .................................................................................................................... 189

Table 140 FW Update Disable .............................................................................................................................. 190

Table 141 RPMB Partition Size ............................................................................................................................ 190

Table 142 Write reliability setting ........................................................................................................................ 191

Table 143 Write reliability parameter register ...................................................................................................... 192

Table 144 Background operations enable ............................................................................................................. 192

Table 145 H/W reset function ............................................................................................................................... 193

Table 146 HPI management ................................................................................................................................. 193

Table 147 Partitioning Support ............................................................................................................................. 194

Table 148 Max. Enhanced Area Size .................................................................................................................... 194

Table 149 Partitions Attribute ............................................................................................................................... 195

Table 150 Partition Setting ................................................................................................................................... 195

Table 151 General Purpose Partition Size ............................................................................................................ 196

Table 152 Enhanced User Data Area Size ............................................................................................................ 197

Table 153 Enhanced User Data Start Address ...................................................................................................... 197

Table 154 Secure Bad Block management ........................................................................................................... 197

Table 155 PRODUCTION_STATE_AWARENESS states ................................................................................. 198

Table 156 CMD26 and CMD27 in DDR mode Support ....................................................................................... 199

Table 157 Initialization Time out value ................................................................................................................ 200

Table 158 Class 6 usage........................................................................................................................................ 200

Table 159 EXCEPTION_EVENTS_CTRL[56] ................................................................................................... 200

Table 160 EXCEPTION_EVENTS_CTRL[57] ................................................................................................... 200

Table 161 EXCEPTION_EVENTS_STATUS[54] .............................................................................................. 201

Table 162 EXCEPTION_EVENT_STATUS[55]................................................................................................. 201

Table 163 First Byte EXT_PARTITIONS_ATTRIBUTE[52] ............................................................................. 201

Table 164 Second Byte EXT_PARTITIONS_ATTRIBUTE[53] ........................................................................ 201

Table 165 CONTEXT_CONF configuration format ............................................................................................ 202

Table 166 Packed Command Status Register ....................................................................................................... 202

Table 167 Valid POWER_OFF_NOTIFICATION values ................................................................................... 203

Table 168 CACHE ENABLE ............................................................................................................................... 203

Table 169 FLUSH CACHE .................................................................................................................................. 204

Table 170 Valid MODE_CONFIG values ............................................................................................................ 204

Table 171 Valid MODE_OPERATION_CODES values ..................................................................................... 204

Table 172 FFU Status codes ................................................................................................................................. 205

Table 173 Secure Removal Type .......................................................................................................................... 207

Table 174 Error correction codes .......................................................................................................................... 208

Table 175 DSR register content ............................................................................................................................ 218

JEDEC Standard No. 84-B50

-xvi-

Contents (cont'd)

Page

Table 176 General operating conditions ............................................................................................................... 220

Table 177 e•MMC power supply voltage ............................................................................................................. 222

Table 178 e•MMC voltage combinations ............................................................................................................. 222

Table 179 Capacitance .......................................................................................................................................... 223

Table 180 Open-drain bus signal level ................................................................................................................. 226

Table 181 Push-pull signal level—high-voltage e•MMC ..................................................................................... 226

Table 182 Push-pull signal level—1.70 -1.95 VCCQ voltage Range ................................................................... 226

Table 183 Push-pull signal level—1.1V-1.3V VCCQ range e•MMC .................................................................. 226

Table 184 I/O driver strength types ...................................................................................................................... 227

Table 185 Driver Type-0 AC Characteristics ...................................................................................................... 228

Table 186 High-speed Device interface timing .................................................................................................... 229

Table 187 Backward-compatible Device interface timing .................................................................................... 230

Table 188 High-speed dual rate interface timing .................................................................................................. 232

Table 189 HS200 Clock signal timing .................................................................................................................. 233

Table 190 HS200 Device input timing ................................................................................................................. 234

Table 191 Output timing ....................................................................................................................................... 235

Table 192 Temperature Conditions ...................................................................................................................... 236

Table 193 HS400 Device input timing ................................................................................................................. 237

Table 194 HS400 Device Output timing............................................................................................................... 238

Table 195 HS400 Capacitance .............................................................................................................................. 239

Table 196 e•MMC host requirements for Device classes ..................................................................................... 241

Table 197 New Features List for device type ....................................................................................................... 242

Table 198 Macro commands ................................................................................................................................. 245

Table 199 Forward-compatible host interface timing ........................................................................................... 255

Table 200 Bus testing for eight data lines ............................................................................................................. 258

Table 201 Bus testing for four data lines .............................................................................................................. 258

Table 202 Bus testing for one data line................................................................................................................. 258

Table 203 XNOR values ....................................................................................................................................... 259

Table 204 Package Case Temp (Tc) per current consumption ............................................................................. 265

剩余295页未读，继续阅读

Moolovey

粉丝: 0
资源: 1

eMMC 5.0标准：JESD84-B50：移动设备的高性能存储解决方案

"eMMC协议5.0原版JESD84-B50.pdf详解及标准解读

eMMC 5.0电气接口标准JESD84-B50：设计指南与工具集

JESD84-B50(eMMC-Spec-V5.0): Linux eMMC驱动开发关键标准文档

eMMC5.0Spec_JESD84-B50

JESD84-B50(eMMC-Spec-V5.0).pdf

JESD84-B50 emmc5.0 协议 英文原档.pdf

JESD84-B451(eMMC-Spec-V4.5.1).pdf

EMMC 5.0 Spec

JESD84-B51.pdf

emmc 5.1 spec

最新资源

JESD84-B50 emmc5.0 协议英文原档.pdf