深度学习FSMC接口配置技术：回波抵消芯片Zarlink的应用

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ZL50232 Data Sheet

Zarlink Semiconductor Inc.

NC A14, C15, D1, D15, E1,

F1, G1, G15, H1, H15,

J1, J15, K1,

K15,L1,L15,F2,L2

24, 25, 26,

44, 45, 46,

47, 49, 51,

52, 53, 54,

55, 73, 74,

75, 76, 78,

79, 80, 82,

83, 84, 85,

89, 99, 50

No connection. These pins must be left open for normal

operation.

IRQ

R9 9

Interrupt Request (Open Drain Output).

This output goes low

when an interrupt occurs in any channel. IRQ returns high when

all the interrupts have been read from the Interrupt FIFO

R11 10 Data Strobe (Input). This active low input works in conjunction

with CS

to enable the read and write operations.

R13 11 Chip Select (Input). This active low input is used by a

microprocessor to activate the microprocessor port.

R/W

R5 12 Read/Write (Input). This input controls the direction of the data

bus lines (D7-D0) during a microprocessor access.

DTA

R7 13 Data Transfer Acknowledgment (Open Drain Output). This

active low output indicates that a data bus transfer is completed.

A pull-up resistor (1 K typical) is required at this output.

D0..D7 T2,T4,T6,T8,T9,T11,

T13,T15

15, 16, 17,

19, 20, 21,

22, 23

Data Bus D0 - D7 (Bidirectional). These pins form the 8 bit

bidirectional data bus of the microprocessor port.

A0..A10 P16,N16,M16,L16,K16,

J16,H16,G16,F16,E16,

D16

28, 29, 30,

31, 33, 34,

35, 36, 38,

39, 40

Address A0 to A10 (Input). These inputs provide the A10 - A0

address lines to the internal registers.

ODE B13 57 Output Drive Enable (Input). This input pin is logically AND’d

with the ODE bit-6 of the Main Control Register. When both ODE

bit and ODE input pin are high, the Rout and Sout ST-BUS

outputs are enabled.

When the ODE bit is low or the ODE input pin is low, the Rout

and Sout ST-BUS outputs are high impedance.

Sout A8 58 Send PCM Signal Output (Output). Port 1 TDM data output

streams. Sout pin outputs serial TDM data streams at

2.048 Mbps with 32 channels per stream.

Rout B9 59 Receive PCM Signal Output (Output). Port 2 TDM data output

streams. Rout pin outputs serial TDM data streams at

2.048 Mbps with 32 channels per stream.

Sin B11 60 Send PCM Signal Input (Input). Port 2 TDM data input streams.

Sin pin receives serial TDM data streams at 2.048 Mbps with 32

channels per stream.

Pin Description (continued)

Name

Pin #

Description

208-Ball LBGA

100 Pin

LQFP

ZL50232 Data Sheet

Zarlink Semiconductor Inc.

Rin B7 61 Receive PCM Signal Input (Input). Port 1 TDM data input

streams. Rin pin receives serial TDM data streams at

2.048 Mbps with 32 channels per stream.

F0i

B5 62 Frame Pulse (Input). This input accepts and automatically

identifies frame synchronization signals formatted according to

ST-BUS or GCI interface specifications.

C4i

A4 63 Serial Clock (Input). 4.096 MHz serial clock for shifting data

in/out on the serial streams (Rin, Sin, Rout, Sout).

MCLK G2 90 Master Clock (Input). Nominal 10 MHz or 20 MHz Master Clock

input. May be connected to an asynchronous (relative to frame

signal) clock source.

Fsel H2 92 Frequency select (Input). This input selects the Master Clock

frequency operation. When Fsel pin is low, nominal 19.2 MHz

Master Clock input must be applied. When Fsel pin is high,

nominal 9.6 MHz Master Clock input must be applied.

PLLVss1

PLLVss2

K3 97, 95 PLL Ground. Must be connected to V

PLLV

K4 96 PLL Power Supply. Must be connected to V

DD2

= 1.8 V

TMS M2 1 Test Mode Select (3.3 V Input). JTAG signal that controls the

state transitions of the TAP controller. This pin is pulled high by

an internal pull-up when not driven.

TDI M1 2 Test Serial Data In (3.3 V Input). JTAG serial test instructions

and data are shifted in on this pin. This pin is pulled high by an

internal pull-up when not driven.

TDO N1 3 Test Serial Data Out (Output). JTAG serial data is output on this

pin on the falling edge of TCK. This pin is held in high impedance

state when JTAG scan is not enabled.

TCK P1 4 Test Clock (3.3 V Input). Provides the clock to the JTAG test

logic.

TRST

N2 6 Test Reset (3.3 V Input). Asynchronously initializes the JTAG

TAP controller by putting it in the Test-Logic-Reset state. This pin

should be pulsed low on power-up or held low, to ensure that the

ZL50232 is in the normal functional mode. This pin is pulled by

an internal pull-down when not driven.

RESET

R3 8 Device Reset (Schmitt Trigger Input). An active low resets the

device and puts the ZL50232 into a low-power stand-by mode.

When the RESET

pin is returned to logic high and a clock is

applied to the MCLK pin, the device will automatically execute

initialization routines, which preset all the Main Control and

Status Registers to their default power-up values.

Pin Description (continued)

Name

Pin #

Description

208-Ball LBGA

100 Pin

LQFP

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