TLV320ADC3101-Q1：低功耗立体声ADC，适用于无线音频设备

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"TI-TLV320ADC3101-Q1.pdf 是一款低功耗立体声数模转换器(ADC)，适用于无线电话耳机、便携式音频设备以及内置小型数字信号处理器(miniDSP)的应用。它具备汽车级标准，满足在-40℃至+105℃环境温度下的工作需求。该器件采用4mmx4mm的24引脚RGE QFN封装，具有良好的ESD防护等级。" **TLV320ADC3101-Q1主要特性:** 1. **电源兼容性** - 模拟电源工作电压范围为2.6V-3.6V，数字内核工作电压为1.65V-1.95V，I/O电压则在1.1V-3.6V之间。 2. **汽车级应用** - 设计符合汽车应用的要求，确保在极端环境下的稳定性能。 3. **AEC-Q100测试** - 经过严格的AEC-Q100测试，包括针对人体模型(HBM)和充电器件模型(CDM)的静电放电(ESD)分类，分别达到H1C和C3B等级。 4. **封装形式** - 使用4mmx4mm的24引脚RGE QFN封装，体积小巧，适合空间有限的设备。 5. **工作温度范围** - 能在-40℃至+105℃的温度范围内正常工作，适应广泛的应用场景。 6. **ESD防护** - 提供高等级的ESD保护，增强了器件的可靠性。 7. **高信噪比** - 提供高达92dBA的信噪比，确保音频质量清晰。 8. **宽范围采样率** - 支持8kHz到96kHz的ADC采样率，适用于多种音频标准。 9. **集成miniDSP** - 内置可编程的miniDSP，用于数字音频的前端处理或语音处理，提供灵活的音频处理能力。 10. **RAM编程** - 配备RAM，允许用户编程系数、指令，并包含内置处理块，提高了系统的可配置性和功能。 **应用领域:** - **无线手持终端** - 适用于无线耳机和蓝牙音频设备，提供高质量的音频输出。 - **便携式音频系统** - 低功耗设计适合移动设备，如MP3播放器、智能手机和便携式媒体播放器。 - **语音处理** - 通过其内置的处理功能，可以用于语音识别、语音增强等应用。 - **音频信号处理** - 可与外部数字信号处理器配合，实现复杂的声音优化和效果处理。 TLV320ADC3101-Q1是一款高性能、低功耗、小巧且适应性强的立体声ADC，适合于各种对音频质量和功耗有高要求的无线及便携式音频产品。其灵活性和嵌入式处理能力使其成为音频解决方案的理想选择。

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TLV320ADC3101-Q1

ZHCS788B –MARCH 2012–REVISED AUGUST 2012

www.ti.com.cn

OVERVIEW

The TLV320ADC3101-Q1 is a flexible, low-power, stereo audio ADC device with extensive feature integration,

intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment

applications. The device integrates a host of features to reduce cost, board space, and power consumption in

space-constrained, battery-powered, portable applications.

The TLV320ADC3101-Q1 consists of the following blocks:

• Stereo audio multibit delta-sigma ADC (8 kHz–96 kHz)

• Programmable digital audio effects processing (3-D, bass, treble, mid-range, EQ, de-emphasis)

• Register-configurable combinations of up to six single-ended or three differential audio inputs

• Fully programmable PLL with extensive ADC clock-source and divider options for maximum end-system

design flexibility

Communication to the TLV320ADC3101-Q1 for control is via a two-wire I

C interface. The I

C interface supports

both standard and fast communication modes.

HARDWARE RESET

The TLV320ADC3101-Q1 requires a hardware reset after power up for proper operation. After all power supplies

are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not

performed, the TLV320ADC3101-Q1 may not respond properly to register reads/writes.

PLL START-UP

When the PLL is powered on, a start-up delay of approximately 10 ms occurs after the power-up command of the

PLL and before the clocks are available to the TLV320ADC3101-Q1. This delay is to ensure stable operation of

the PLL and clock-divider logic.

SOFTWARE POWER DOWN

By default, all circuit blocks are powered down following a reset condition. Hardware power up of each circuit

block can be controlled by writing to the appropriate control register. This approach allows the lowest power-

supply current for the functionality required. However, when a block is powered down, all of the register settings

are maintained as long as power is still being applied to the device.

miniDSP

The TLV320ADC3101-Q1 features a miniDSP core which is tightly coupled to the ADC. The fully programmable

algorithms for the miniDSP must be loaded into the device after power up. The miniDSP has direct access to the

digital stereo audio stream, offering the possibility for advanced, very low-group-delay DSP algorithms. The ADC

miniDSP has 512 programmable instructions, 256 data memory locations, and 128 programmable coefficients.

Software development for the TLV320ADC3101-Q1 is supported through TI's comprehensive PurePath™ Studio

software development environment, a powerful, easy-to-use tool designed specifically to simplify software

development on Texas Instruments miniDSP audio platforms. The graphical development environment consists

of a library of common audio functions that can be dragged and dropped into an audio signal flow and graphically

connected together. The DSP code can then be assembled from the graphical signal flow with the click of a

mouse. See the TLV320ADC3101-Q1 product folder on www.ti.com to learn more about PurePath Studio

software and the latest status on available, ready-to-use DSP algorithms.

DIGITAL CONTROL SERIAL INTERFACE

C CONTROL MODE

The TLV320ADC3101-Q1 supports the I

C control protocol and is capable of both standard and fast modes.

Standard mode is up to 100 kHz and fast mode is up to 400 kHz. When in I

C control mode, the

TLV320ADC3101-Q1 can be configured for one of four different addresses, using the pins I2C_ADR1 and

I2C_ADR0, which control the two LSBs of the device address. The 5 MSBs of the device address are fixed as

0011 0 and cannot be changed, while the two LSBs are given by I2C_ADR1:I2C_ADR0. This results in four

possible device addresses:

TLV320ADC3101-Q1

www.ti.com.cn

ZHCS788B –MARCH 2012–REVISED AUGUST 2012

Table 2. I

C Slave Device Addresses for I2C_ADR1, I2C_ADR0 Settings

I2C_ADR1 I2C_ADR0 Device Address

0 0 0011 000

0 1 0011 001

1 0 0011 010

1 1 0011 011

C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the

C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.

Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving

them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver

contention.

Communication on the I

C bus always takes place between two devices, one acting as the master and the other

acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of

the master. Some I

C devices can act as masters or slaves, but the TLV320ADC3101-Q1 can only act as a slave

device.

An I

C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted

across the I

C bus in groups of eight bits. To send a bit on the I

C bus, the SDA line is driven to the appropriate

level while SCL is LOW (a LOW on SDA indicates the bit is 0; a HIGH indicates the bit is 1). Once the SDA line

has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receiver

shift register.

The I

C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads

from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line.

Under normal circumstances, the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When

communication is taking place, the bus is active. Only master devices can start a communication. They do this by

causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock

line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its

counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from

HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates the slave device with which it is to

communicate. This byte is called the address byte. Each device on an I

C bus has a unique 7-bit address to

which it responds. (Slaves can also have 10-bit addresses; see the I

C specification for details.) The master

sends an address in the address byte, together with a bit that indicates whether it is to read from or write to the

slave device.

Every byte transmitted on the I

C bus, whether it is address or data, is acknowledged with an acknowledge bit.

When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the

slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a

clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW

to acknowledge this to the slave. It then sends a clock pulse to clock the bit.

A not-acknowledge is performed by leaving SDA HIGH during an acknowledge cycle. If a device is not present

on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at

that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP

condition is issued, the bus becomes idle again. A master may also issue another START condition. When a

START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320ADC3101-Q1 also responds to and acknowledges a general call, which consists of the master

issuing a command with a slave address byte of 00h.

DA(6) DA(0) RA(7) RA(0)

Start

(M)

7-bit Device Address

(M)

Write

(M)

Slave

Ack

(S)

8-bit Register Address

(M)

Slave

Ack

(S)

SDA

SCL

DA(6) DA(0)

7-bit Device Address

(M)

Read

(M)

Slave

Ack

(S)

D(7) D(0)

8-bit Register Data

(S)

Stop

(M)

Master

No Ack

(M)

Repeat

Start

(M)

(M) => SDA Controlled by Master

(S) => SDA Controlled by Slave

DA(6) DA(0) RA(7) RA(0) D(7) D(0)

Start

(M)

7-bit Device Address

(M)

Write

(M)

Slave

Ack

(S)

8-bit Register Address

(M)

Slave

Ack

(S)

8-bit Register Data

(M)

Stop

(M)

Slave

Ack

(S)

SDA

SCL

(M) => SDA Controlled by Master

(S) => SDA Controlled by Slave

TLV320ADC3101-Q1

ZHCS788B –MARCH 2012–REVISED AUGUST 2012

www.ti.com.cn

Figure 12. I

C Write

Figure 13. I

C Read

In the case of an I

C register write, if the master does not issue a STOP condition, then the device enters auto-

increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I

C register read, after the device has sent out the 8-bit data from the addressed

next eight clocks the data of the next incremental register.

DIGITAL AUDIO DATA SERIAL INTERFACE

Audio data is transferred between the host processor and the TLV320ADC3101-Q1 via the digital-audio serial-

data interface, or audio bus. The audio bus on this device is flexible, including left- or right-justified data options,

support for I

S or PCM protocols, programmable data-length options, a TDM mode for multichannel operation,

flexible master/slave configurability for each bus clock line, and the ability to communicate with multiple devices

within a system directly.

The audio serial interface on the TLV320ADC3101-Q1 has an extensive I/O control to allow for communicating

with two independent processors for audio data. The processors can communicate with the device one at a time.

This feature is enabled by register programming of the various pin selections.

The audio bus of the TLV320ADC3101-Q1 can be configured for left- or right-justified, I

S, DSP, or TDM modes

of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.

These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits by configuring page 0 /

master or slave mode for flexible connectivity to a wide variety of processors. The word clock is used to define

the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of

this clock corresponds to the maximum of the selected ADC sampling frequencies.

The bit clock is used to clock in and out the digital audio data across the serial bus. When in master mode, this

signal can be programmed to generate variable clock pulses by controlling the bit-clock divider in page 0 /

TLV320ADC3101-Q1s share the same audio bus may require that the number of bit-clock pulses in a frame be

adjusted.

The TLV320ADC3101-Q1 also includes a feature to offset the position of the start of data a transfer with respect

to the word clock. There are two configurations that afford the user to use either a single offset for both channels

or to use separate offsets. Ch_Offset_1 reference represents the value in page 0 / register 28 and Ch_Offset_2

represents the value in page 0 / register 37. When page 0 / register 38, bit D0 is set to zero (time-slot-based

channel assigment is disabled), the offset of both channels is controlled, in terms of number of bit clocks, by the

programming in page 0 / register 28 (Ch_Offset_1). When page 0 / register 38, bit D0 = 1 (time-slot-based

WCLK

BCLK

DOUT

‘0’ ‘0’ ‘0’

‘0’

R-2 2 1 0X R-1 X

1/fs

FrameTime/2

DOUT_Tristate

3 N

WCLK

BCLK

DOUT

N -1 N -2 N - 01 N -2 -3 2 1 0X N -1 X

1/fs

DOUT_Tristate

TLV320ADC3101-Q1

www.ti.com.cn

ZHCS788B –MARCH 2012–REVISED AUGUST 2012

channel assignment enabled), the first channel is controlled, in terms of number of bit clocks, by the

programming in page 0 / register 28 (Ch_Offset_1), and the second channel is controlled, in terms of number of

bit clocks, by the programming in page 0 / register 37 (Ch_Offset_2), where register 37 programs the delay

between the first word and the second word. Also, the relative order of the two channels can be swapped,

depending on the programmable register bit (page 0 / register 38, bit D4) that enables swapping of the channels.

The TLV320ADC3101-Q1 also supports a feature of inverting the polarity of bit clock used for transferring the

audio data as compared to the default clock polarity used. This feature can be used independently of the mode

of audio interface chosen. This can be configured by writing to page 0 / register 29, bit D3.

The TLV320ADC3101-Q1 further includes programmability (page 0 / register 27, bit D0) to place DOUT in the

high-impedance state at the end of data transfer (i.e., at the end of the bit cycle corresponding to the LSB of a

channel). By combining this capability with the ability to program at what bit clock in a frame the audio data

begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple ADCs able to use a single

audio serial data bus. To further enhance the 3-state capability, the TLV320ADC3101-Q1 can be put in a high-

impedance state a half bit cycle earlier by setting page 0 / register 38, bit D1 to 1. When the audio serial data

bus is powered down while configured in master mode, the pins associated with the interface are put into a high-

impedance output state.

Figure 14. Both Channels Enabled, Early 3-Stating Enabled

Either or both of the two channels can be disabled in LJF, I

S, and DSP modes by using page 0 / register 38,

bits D3–D2. Figure 14 shows the interface timing when both channels are enabled and early 3-stating is enabled.

Figure 15 shows the effect of setting page 0 / register 38, bit D2, first channel disabled, and setting page 0 /

impedance state is disabled, then the DOUT signal is driven to logic level 0.

Figure 15. First Channel Disabled, Second Channel Enabled, 3-Stating Enabled

The sync signal for the ADC filter is not generated based on the disabled channel. The sync signal for the filter

corresponds to the beginning of the earlier of the two channels. If the first channel is disabled, the filter sync is

generated at the beginning of the second channel, if it is enabled. If both the channels are disabled, there is no

output to the serial bus, and the filter sync corresponds to the beginning of the frame.

By default, when the word clocks and bit clocks are generated by the TLV320ADC3101-Q1, these clocks are

active only when the ADC is powered up within the device. This is done to save power. However, it also supports

a feature wherein both the word clocks and bit clocks can be active even when the codec in the device is

powered down. This is useful when using the TDM mode with multiple codecs on the same bus or when word

clocks or bit clocks are used in the system as general-purpose clocks.

Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling

edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding

the rising edge of the word clock. See Figure 16 for right-justifed mode timing.

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