TI-BUF20800：高级TFT-LCD面板的可编程电压参考解决方案

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TI-BUF20800是一款专为TFT-LCD面板设计的可编程电压参考发生器，其主要特点包括： 1. **18通道γ校正**：该器件提供了18个独立可编程输出通道，用于精确调整gamma曲线，以改善液晶显示器的图像质量。这极大地简化了传统方法中通过调整电阻值来优化不同gamma电压的过程。 2. **2个可编程VCOM通道**：除了gamma校正通道外，还有两个VCOM（Video Commutation Voltage）通道，每个通道都具备10位分辨率，允许设计师灵活地调节液晶面板的垂直同步控制电压，以实现最佳显示效果。 3. **低功耗设计**：BUF20800的工作电流非常低，仅为每通道900微安，这对于电源效率和系统整体功耗管理至关重要。 4. **宽工作电压范围**：输入供电电压支持从7V到18V，而数字供电范围为2.0V到5.5V，确保了设备在各种应用环境中的稳定运行。 5. **标准接口**：采用工业标准的两线接口，最高传输速率为3.4MHz，方便与外围设备通信。 6. **高ESD保护**：器件具有出色的抗静电能力，能够承受高达4kV的HBM（人体模型）冲击，1kV的CDM（共模）电压以及200V的MM（蔓越莓）电压，保证了系统的电磁兼容性和安全性。 7. **配备Demo板和软件**：TI提供配套的开发板和相关软件，帮助用户快速集成和测试该芯片，简化设计流程。 8. **输出模式多样**：包含模拟和数字两种类型的输出，如REFH、REFLOUT、DACRegisters等，以满足不同应用场景的需求。 9. **应用广泛**：BUF20800特别适合替换传统的基于电阻的gamma解决方案，适用于对图像质量和响应速度有高要求的TFT-LCD驱动，如动态gamma控制等。 TI-BUF20800是一款高性能且灵活性极高的电压参考发生器，针对TFT-LCD显示系统设计，通过程序化配置功能和高效的硬件特性，提高了设计效率并降低了系统成本。它凭借其广泛的适用性和强大的功能，成为液晶显示领域中的理想选择。

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SBOS329E − JUNE 2005 − REVISED DECEMBER 2007

www.ti.com

APPLICATIONS INFORMATION

The BUF20800 programmable voltage reference allows

fast, easy adjustment of 18 programmable reference

outputs and two channels for V

COM

adjustment, each with

10-bit resolution. It offers very simple, time-efficient

adjustment of the gamma reference and V

COM

voltages.

The BUF20800 is programmed through a high-speed,

standard, two-wire interface. The BUF20800 features a

double-register structure for each DAC channel to simplify

the implementation of dynamic gamma control. This

structure allows pre-loading of register data and rapid

updating of all channels simultaneously.

Buffers 1−9 are able to swing to within 200mV of the

positive supply rail, and to within 0.6V of the negative

supply rail. Buffers 10−18 are able to swing to within 0.8V

of the positive supply rail and to within 200mV of the

negative supply rail.

The BUF20800 can be powered using an analog supply

voltage from 7V to 18V, and a digital supply from 2V to

5.5V. The digital supply must be applied prior to or

simultaneously with the analog supply to avoid excessive

current and power consumption; damage to the device

may occur if it is left connected only to the analog supply

for extended periods of time. Figure 7 shows the power

supply timing requirements.

GND

Digital Supply:

Analog Supply:

: 0s minimum delay between Digital Supply and Analog Supply.

Figure 7. Power Supply Timing Requirements

Figure 8 shows the BUF20800 in a typical configuration.

In this configuration, the BUF20800 device address is 74h.

The output of each digital-to-analog converter (DAC) is

immediately updated as soon as data are received in the

corresponding register (LD = 0). For maximum dynamic

range, set V

REFH

= V

− 0.2V and V

REFL

= GND + 0.2V.

TWO-WIRE BUS OVERVIEW

The BUF20800 communicates through an industry-

standard, two-wire interface to receive data in slave mode.

This standard uses a two-wire, open-drain interface that

supports multiple devices on a single bus. Bus lines are

driven to a logic low level only. The device that initiates the

communication is called a master, and the devices

controlled by the master are slaves. The master generates

the serial clock on the clock signal line (SCL), controls the

bus access, and generates the START and STOP

conditions.

To address a specific device, the master initiates a START

condition by pulling the data signal line (SDA) from a HIGH

to a LOW logic level while SCL is HIGH. All slaves on the

bus shift in the slave address byte, with the last bit

indicating whether a read or write operation is intended.

During the 9th clock pulse, the slave being addressed

responds to the master by generating an Acknowledge

and pulling SDA LOW.

Data transfer is then initiated and eight bits of data are sent

followed by an Acknowledge Bit. During data transfer,

SDA must remain stable while SCL is HIGH. Any change

in SDA while SCL is HIGH will be interpreted as a START

or STOP condition.

Once all data has been transferred, the master generates

a STOP condition indicated by pulling SDA from LOW to

HIGH while SCL is HIGH.

The BUF20800 can act only as a slave device; therefore,

it never drives SCL. SCL is only an input for the BUF20800.

Table 1 and Table 2 summarize the address and

command codes, respectively, for the BUF20800.

ADDRESSING THE BUF20800

The address of the BUF20800 is 111010x, where x is the

state of the A0 pin. When the A0 pin is LOW, the device will

acknowledge on address 74h (1110100). If the A0 pin is

HIGH, the device will acknowledge on address 75h

(1110101).

Other valid addresses are possible through a simple mask

change. Contact your TI representative for information.

Table 1. Quick-Reference Table of BUF20800

Addresses

DEVICE/COMPONENT ADDRESS

BUF20800 Address:

A0 pin is LOW

(device will acknowledge on address 74h)

1110100

A0 pin is HIGH

(device will acknowledge on address 75h)

1110101

Table 2. Quick-Reference Table of Command

Codes

COMMAND CODE

General Call Reset

Address byte of 00h followed by a data byte

of 06h.

High-Speed Mode

00001xxx, with SCL ≤ 400kHz; where xxx

are bits unique to the Hs-capable master.

This byte is called the Hs master code.

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